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i=@fujitsu.com; q=dns/txt; s=fj2; t=1715129621; x=1746665621; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=Zl5gLii4NnwGLwqVkepmmSn5NlN9z7y1E/Dp0UH+HaM=; b=aMsLGh0N1fCz74TJXge8TwEYH3Nv4s1Hh0fgNXlgiIGEwf2dKjLZvIsa 1/v/WRBQ8WhGQc3+33gzzfcS/efA+glPhGxjV00+Ux39KLDJUD1rnj4Qb PrF7rzQGv8hGo6oqzClH3F9IqhyOORNh6+l630+PuMvxaVxRaQe4u5yuJ ZKYcRu0Y5L3dyZEEaWZ08qd8tU5DnjZqUMufqGzrMswsUmm1qtcQGyv61 h4fAVRnLn28XDp76MfYu+b/MnDWPnfTbX3VMbX7J/F56N1GhRz8fK/jjV +eGkk3sQfXfttCBtBjZXi+xOVRbJHJxpIIVOeRT9yOyC/dkPA07Zg6OkS Q==; X-IronPort-AV: E=McAfee;i="6600,9927,11066"; a="157021519" X-IronPort-AV: E=Sophos;i="6.08,143,1712588400"; d="scan'208";a="157021519" To: jonathan.cameron@huawei.com, fan.ni@samsung.com Cc: qemu-devel@nongnu.org, Yao Xingtao Subject: [PATCH v3] mem/cxl_type3: support 3, 6, 12 and 16 interleave ways Date: Tue, 7 May 2024 20:53:23 -0400 Message-Id: <20240508005323.28811-1-yaoxt.fnst@fujitsu.com> X-Mailer: git-send-email 2.37.3 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-TM-AS-Product-Ver: IMSS-9.1.0.1417-9.0.0.1002-28368.003 X-TM-AS-User-Approved-Sender: Yes X-TMASE-Version: IMSS-9.1.0.1417-9.0.1002-28368.003 X-TMASE-Result: 10--1.421000-10.000000 X-TMASE-MatchedRID: Ugxu9kqXWxKROBVNmXUDuMIkzTqL3E/Wm0H2L3kjQgrn3ZLCt3rRSSNM v5a0AeBD77BjzUhRJQ6Ekl9vR6Agi4KeFxulmNWzCKFDk1kJexL4qCLIu0mtIDoUdFbHYUawvwU evDt+uW5/XjpbSJS7a8uO56bqT71TobdjeDI8cBERW4LR41Fi8gK0ZgbTOeKUCgyP/UnUGw2sk5 e3FzGIt6GvCFqoKSwTgDLqnrRlXrZ8nn9tnqel2MZW5ai5WKlyRPmeB2fP7cVXsITydO8Kq8yZM 0/Lon4PsWTG2IJ/oZuJPdn4GCUY/9intcvwyXiQndQdE21ZNlhZGP6RUrd0AlCVnYtH3p+QEWW0 bEJOTAVAdUD6vW8Z1mZAMQMIyK6zB8/x9JIi8hKhgLRzA45JPQ== X-TMASE-SNAP-Result: 1.821001.0001-0-1-22:0,33:0,34:0-0 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.139.130; envelope-from=yaoxt.fnst@fujitsu.com; helo=esa5.hc1455-7.c3s2.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Yao Xingtao From: Yao Xingtao via Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1715129652576100001 Content-Type: text/plain; charset="utf-8" Since the kernel does not check the interleave capability, a 3-way, 6-way, 12-way or 16-way region can be create normally. Applications can access the memory of 16-way region normally because qemu can convert hpa to dpa correctly for the power of 2 interleave ways, after kernel implementing the check, this kind of region will not be created any more. For non power of 2 interleave ways, applications could not access the memory normally and may occur some unexpected behaviors, such as segmentation fault. So implements this feature is needed. Link: https://lore.kernel.org/linux-cxl/3e84b919-7631-d1db-3e1d-33000f3f386= 8@fujitsu.com/ Signed-off-by: Yao Xingtao --- hw/cxl/cxl-component-utils.c | 9 +++++++-- hw/mem/cxl_type3.c | 15 +++++++++++---- 2 files changed, 18 insertions(+), 6 deletions(-) diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c index cd116c0401..473895948b 100644 --- a/hw/cxl/cxl-component-utils.c +++ b/hw/cxl/cxl-component-utils.c @@ -243,8 +243,13 @@ static void hdm_init_common(uint32_t *reg_state, uint3= 2_t *write_msk, ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, INTERLEAVE_4K,= 1); ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, POISON_ON_ERR_CAP, 0); - ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, 3_6_12_WAY, 0); - ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, 16_WAY, 0); + if (type =3D=3D CXL2_TYPE3_DEVICE) { + ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, 3_6_12_WAY= , 1); + ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, 16_WAY, 1); + } else { + ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, 3_6_12_WAY= , 0); + ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, 16_WAY, 0); + } ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, UIO, 0); ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, UIO_DECODER_COUNT, 0); diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index 3e42490b6c..b755318838 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -804,10 +804,17 @@ static bool cxl_type3_dpa(CXLType3Dev *ct3d, hwaddr h= ost_addr, uint64_t *dpa) continue; } =20 - *dpa =3D dpa_base + - ((MAKE_64BIT_MASK(0, 8 + ig) & hpa_offset) | - ((MAKE_64BIT_MASK(8 + ig + iw, 64 - 8 - ig - iw) & hpa_offset) - >> iw)); + if (iw < 8) { + *dpa =3D dpa_base + + ((MAKE_64BIT_MASK(0, 8 + ig) & hpa_offset) | + ((MAKE_64BIT_MASK(8 + ig + iw, 64 - 8 - ig - iw) & hpa_of= fset) + >> iw)); + } else { + *dpa =3D dpa_base + + ((MAKE_64BIT_MASK(0, 8 + ig) & hpa_offset) | + ((((MAKE_64BIT_MASK(ig + iw, 64 - ig - iw) & hpa_offset) + >> (ig + iw)) / 3) << (ig + 8))); + } =20 return true; } --=20 2.37.3