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([149.14.240.163]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42013c5fa61sm132080825e9.40.2024.05.15.08.08.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 May 2024 08:08:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1715785728; x=1716390528; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8W7kdXBVphE/G8J+gJEIX1gz3O6+dJRyyNI2VZW5z4A=; b=MT8p7SnF6YcdPyP2SRVhF7e3k2T7a3ndnZZdaXC9O8tdaYWwbhE+47NcukEzbkm6Qb 9v+nn7xwvdIEnjz7IP+JHmjc6zrwO78qqUKrHXvzbtZ4V2hE7mF7cij5wDlueJ71TCqd sNcEm0zrcYGkXwwXcGP2wLZIaec3qEgQQtMJ5B/LvSw7dn0K4M2o5zn1Y9OFmSH7mDUe bVRlN6k9Davz0OD8tCXg1Q1FVi9S0u7Dw5z6gEn36jLCmerwSti9ezY4l9PJUgz41LMZ srrtx4UUFWhcjJU0Ery10nvqe4v4aDUqgsJVVGoLqm62tzb7veB7t2jhkWcJwUlH3/2q xSRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715785728; x=1716390528; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8W7kdXBVphE/G8J+gJEIX1gz3O6+dJRyyNI2VZW5z4A=; b=feag4mSshcN/LEFp7si1K57SHu2IB3kLBatje1cX5DJ8h9TKebJXFiRu7HaAOcHmPi kipWB0deQkCI+uTzHaZpNLSN2OlK2Cv/7uO0IU/pMJJGlRLMsWOehAx0sXre8xwkfCB5 PhHP/EgEfTA1BE8Qkc2/47PYAEF+tPo9/X/sgPqoFXGuNlkBpAtIWTVgqTakpZ+O9xQ1 e6fJAeE9S3fNq4zTA1Ct8t/OKMR1lBxOvixR//zMHSBGXqqvc38S1cxSpDGFBjsP3DET ZaYxDLqGq2RAQLSJecgB6I5/qLfBSXzzYejwYZ9/qiUexVOXALoz5hbSPY/pfr9NX5hD tGwQ== X-Gm-Message-State: AOJu0Yw/l0IrTlZzndTRMTjbjSG2W3XI4WJrpDLW9O5yQRQRs2mehdPT ixYhmNGmubBVPNy8IAim33brzsKnTTRB+c0Ad6dR9BL4B0dlr3IkWVWSUr1VpSR5+BeeqPHKKKd NQxk= X-Google-Smtp-Source: AGHT+IGmfqiTzkYKr4MqHX4f3/+/x4OBnWowk1fAOG/K9ahQgVfqAdhuCNwZkH5Jx/BsYY+RxWlkrQ== X-Received: by 2002:a05:600c:3c83:b0:41b:8041:53c2 with SMTP id 5b1f17b1804b1-41feac51e04mr161177545e9.15.1715785727847; Wed, 15 May 2024 08:08:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, laurent@vivier.eu Subject: [PATCH v3 10/28] target/i386: Convert do_xsave_* to X86Access Date: Wed, 15 May 2024 17:08:19 +0200 Message-Id: <20240515150837.259747-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240515150837.259747-1-richard.henderson@linaro.org> References: <20240515150837.259747-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1715785885558100003 Content-Type: text/plain; charset="utf-8" The body of do_xsave is now fully converted. Reviewed-by: Paolo Bonzini Signed-off-by: Richard Henderson --- target/i386/tcg/fpu_helper.c | 47 ++++++++++++++++++++---------------- 1 file changed, 26 insertions(+), 21 deletions(-) diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index 4dcb0b92ff..356397a4ab 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -2579,8 +2579,9 @@ static void do_xsave_sse(X86Access *ac, target_ulong = ptr) } } =20 -static void do_xsave_ymmh(CPUX86State *env, target_ulong ptr, uintptr_t ra) +static void do_xsave_ymmh(X86Access *ac, target_ulong ptr) { + CPUX86State *env =3D ac->env; int i, nb_xmm_regs; =20 if (env->hflags & HF_CS64_MASK) { @@ -2590,33 +2591,36 @@ static void do_xsave_ymmh(CPUX86State *env, target_= ulong ptr, uintptr_t ra) } =20 for (i =3D 0; i < nb_xmm_regs; i++, ptr +=3D 16) { - cpu_stq_data_ra(env, ptr, env->xmm_regs[i].ZMM_Q(2), ra); - cpu_stq_data_ra(env, ptr + 8, env->xmm_regs[i].ZMM_Q(3), ra); + access_stq(ac, ptr, env->xmm_regs[i].ZMM_Q(2)); + access_stq(ac, ptr + 8, env->xmm_regs[i].ZMM_Q(3)); } } =20 -static void do_xsave_bndregs(CPUX86State *env, target_ulong ptr, uintptr_t= ra) +static void do_xsave_bndregs(X86Access *ac, target_ulong ptr) { + CPUX86State *env =3D ac->env; target_ulong addr =3D ptr + offsetof(XSaveBNDREG, bnd_regs); int i; =20 for (i =3D 0; i < 4; i++, addr +=3D 16) { - cpu_stq_data_ra(env, addr, env->bnd_regs[i].lb, ra); - cpu_stq_data_ra(env, addr + 8, env->bnd_regs[i].ub, ra); + access_stq(ac, addr, env->bnd_regs[i].lb); + access_stq(ac, addr + 8, env->bnd_regs[i].ub); } } =20 -static void do_xsave_bndcsr(CPUX86State *env, target_ulong ptr, uintptr_t = ra) +static void do_xsave_bndcsr(X86Access *ac, target_ulong ptr) { - cpu_stq_data_ra(env, ptr + offsetof(XSaveBNDCSR, bndcsr.cfgu), - env->bndcs_regs.cfgu, ra); - cpu_stq_data_ra(env, ptr + offsetof(XSaveBNDCSR, bndcsr.sts), - env->bndcs_regs.sts, ra); + CPUX86State *env =3D ac->env; + + access_stq(ac, ptr + offsetof(XSaveBNDCSR, bndcsr.cfgu), + env->bndcs_regs.cfgu); + access_stq(ac, ptr + offsetof(XSaveBNDCSR, bndcsr.sts), + env->bndcs_regs.sts); } =20 -static void do_xsave_pkru(CPUX86State *env, target_ulong ptr, uintptr_t ra) +static void do_xsave_pkru(X86Access *ac, target_ulong ptr) { - cpu_stq_data_ra(env, ptr, env->pkru, ra); + access_stq(ac, ptr, ac->env->pkru); } =20 static void do_fxsave(X86Access *ac, target_ulong ptr) @@ -2669,6 +2673,7 @@ static void do_xsave(CPUX86State *env, target_ulong p= tr, uint64_t rfbm, { uint64_t old_bv, new_bv; X86Access ac; + unsigned size; =20 /* The OS must have enabled XSAVE. */ if (!(env->cr[4] & CR4_OSXSAVE_MASK)) { @@ -2684,8 +2689,8 @@ static void do_xsave(CPUX86State *env, target_ulong p= tr, uint64_t rfbm, rfbm &=3D env->xcr0; opt &=3D rfbm; =20 - access_prepare(&ac, env, ptr, sizeof(X86LegacyXSaveArea), - MMU_DATA_STORE, ra); + size =3D xsave_area_size(opt, false); + access_prepare(&ac, env, ptr, size, MMU_DATA_STORE, ra); =20 if (opt & XSTATE_FP_MASK) { do_xsave_fpu(&ac, ptr); @@ -2698,22 +2703,22 @@ static void do_xsave(CPUX86State *env, target_ulong= ptr, uint64_t rfbm, do_xsave_sse(&ac, ptr); } if (opt & XSTATE_YMM_MASK) { - do_xsave_ymmh(env, ptr + XO(avx_state), ra); + do_xsave_ymmh(&ac, ptr + XO(avx_state)); } if (opt & XSTATE_BNDREGS_MASK) { - do_xsave_bndregs(env, ptr + XO(bndreg_state), ra); + do_xsave_bndregs(&ac, ptr + XO(bndreg_state)); } if (opt & XSTATE_BNDCSR_MASK) { - do_xsave_bndcsr(env, ptr + XO(bndcsr_state), ra); + do_xsave_bndcsr(&ac, ptr + XO(bndcsr_state)); } if (opt & XSTATE_PKRU_MASK) { - do_xsave_pkru(env, ptr + XO(pkru_state), ra); + do_xsave_pkru(&ac, ptr + XO(pkru_state)); } =20 /* Update the XSTATE_BV field. */ - old_bv =3D cpu_ldq_data_ra(env, ptr + XO(header.xstate_bv), ra); + old_bv =3D access_ldq(&ac, ptr + XO(header.xstate_bv)); new_bv =3D (old_bv & ~rfbm) | (inuse & rfbm); - cpu_stq_data_ra(env, ptr + XO(header.xstate_bv), new_bv, ra); + access_stq(&ac, ptr + XO(header.xstate_bv), new_bv); } =20 void helper_xsave(CPUX86State *env, target_ulong ptr, uint64_t rfbm) --=20 2.34.1