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Date: Mon, 20 May 2024 13:51:56 +0100 Message-Id: <20240520125157.311503-2-rkanwal@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240520125157.311503-1-rkanwal@rivosinc.com> References: <20240520125157.311503-1-rkanwal@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=rkanwal@rivosinc.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1716209570434100001 Content-Type: text/plain; charset="utf-8" AIA extends the width of all IRQ CSRs to 64bit even in 32bit systems by adding missing half CSRs. This seems to be missed while adding support for virtual IRQs. The whole logic seems to be correct except the width of the masks. Fixes: 1697837ed9 ("target/riscv: Add M-mode virtual interrupt and IRQ filt= ering support.") Fixes: 40336d5b1d ("target/riscv: Add HS-mode virtual interrupt and IRQ fil= tering support.") Signed-off-by: Rajnesh Kanwal Reviewed-by: Daniel Henrique Barboza Acked-by: Alistair Francis --- target/riscv/csr.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 6b460ee0e8..152796ebc0 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1200,18 +1200,18 @@ static const target_ulong sstatus_v1_10_mask =3D SS= TATUS_SIE | SSTATUS_SPIE | */ =20 /* Bit STIP can be an alias of mip.STIP that's why it's writable in mvip. = */ -static const target_ulong mvip_writable_mask =3D MIP_SSIP | MIP_STIP | MIP= _SEIP | +static const uint64_t mvip_writable_mask =3D MIP_SSIP | MIP_STIP | MIP_SEI= P | LOCAL_INTERRUPTS; -static const target_ulong mvien_writable_mask =3D MIP_SSIP | MIP_SEIP | +static const uint64_t mvien_writable_mask =3D MIP_SSIP | MIP_SEIP | LOCAL_INTERRUPTS; =20 -static const target_ulong sip_writable_mask =3D SIP_SSIP | LOCAL_INTERRUPT= S; -static const target_ulong hip_writable_mask =3D MIP_VSSIP; -static const target_ulong hvip_writable_mask =3D MIP_VSSIP | MIP_VSTIP | +static const uint64_t sip_writable_mask =3D SIP_SSIP | LOCAL_INTERRUPTS; +static const uint64_t hip_writable_mask =3D MIP_VSSIP; +static const uint64_t hvip_writable_mask =3D MIP_VSSIP | MIP_VSTIP | MIP_VSEIP | LOCAL_INTERRUPTS; -static const target_ulong hvien_writable_mask =3D LOCAL_INTERRUPTS; +static const uint64_t hvien_writable_mask =3D LOCAL_INTERRUPTS; =20 -static const target_ulong vsip_writable_mask =3D MIP_VSSIP | LOCAL_INTERRU= PTS; +static const uint64_t vsip_writable_mask =3D MIP_VSSIP | LOCAL_INTERRUPTS; =20 const bool valid_vm_1_10_32[16] =3D { [VM_1_10_MBARE] =3D true, --=20 2.34.1 From nobody Mon Apr 6 16:17:28 2026 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1716209580; 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Date: Mon, 20 May 2024 13:51:57 +0100 Message-Id: <20240520125157.311503-3-rkanwal@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240520125157.311503-1-rkanwal@rivosinc.com> References: <20240520125157.311503-1-rkanwal@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=rkanwal@rivosinc.com; helo=mail-pl1-x62a.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1716209581853100001 Content-Type: text/plain; charset="utf-8" Qemu maps IRQs 0:15 for core interrupts and 16 onward for guest interrupts which are later translated to hgiep in `riscv_cpu_set_irq()` function. With virtual IRQ support added, software now can fully use the whole local interrupt range without any actual hardware attached. This change moves the guest interrupt range after the core local interrupt range to avoid clash. Fixes: 1697837ed9 ("target/riscv: Add M-mode virtual interrupt and IRQ filt= ering support.") Fixes: 40336d5b1d ("target/riscv: Add HS-mode virtual interrupt and IRQ fil= tering support.") Signed-off-by: Rajnesh Kanwal Acked-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu_bits.h | 3 ++- target/riscv/csr.c | 9 ++++++++- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 74318a925c..a470fda9be 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -695,7 +695,8 @@ typedef enum RISCVException { #define IRQ_M_EXT 11 #define IRQ_S_GEXT 12 #define IRQ_PMU_OVF 13 -#define IRQ_LOCAL_MAX 16 +#define IRQ_LOCAL_MAX 64 +/* -1 is due to bit zero of hgeip and hgeie being ROZ. */ #define IRQ_LOCAL_GUEST_MAX (TARGET_LONG_BITS - 1) =20 /* mip masks */ diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 152796ebc0..464e0e57a3 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1148,7 +1148,14 @@ static RISCVException write_stimecmph(CPURISCVState = *env, int csrno, =20 #define VSTOPI_NUM_SRCS 5 =20 -#define LOCAL_INTERRUPTS (~0x1FFF) +/* + * All core local interrupts except the fixed ones 0:12. This macro is for + * virtual interrupts logic so please don't change this to avoid messing up + * the whole support, For reference see AIA spec: `5.3 Interrupt filtering= and + * virtual interrupts for supervisor level` and `6.3.2 Virtual interrupts = for + * VS level`. + */ +#define LOCAL_INTERRUPTS (~0x1FFFULL) =20 static const uint64_t delegable_ints =3D S_MODE_INTERRUPTS | VS_MODE_INTERRUPTS | MIP_LCOFIP; --=20 2.34.1