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Sat, 08 Jun 2024 01:35:25 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF2ZuUZX650Pn7jZKBJkQKcfPQ3FPeDPLEc7r9MB9xc2eYJkLVqjR9uplLvNwr8xAiMv9FfWg== X-Received: by 2002:a50:8d01:0:b0:57c:61a3:54c with SMTP id 4fb4d7f45d1cf-57c61a30661mr1605684a12.0.1717835724650; Sat, 08 Jun 2024 01:35:24 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Phil Dennis-Jordan , Roman Bolshakov Subject: [PULL 25/42] i386/hvf: Adds support for INVTSC cpuid bit Date: Sat, 8 Jun 2024 10:33:58 +0200 Message-ID: <20240608083415.2769160-26-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240608083415.2769160-1-pbonzini@redhat.com> References: <20240608083415.2769160-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1717835972932100009 Content-Type: text/plain; charset="utf-8" From: Phil Dennis-Jordan This patch adds the INVTSC bit to the Hypervisor.framework accelerator's CPUID bit passthrough allow-list. Previously, specifying +invtsc in the CPU configuration would fail with the following warning despite the host CPU advertising the feature: qemu-system-x86_64: warning: host doesn't support requested feature: CPUID.80000007H:EDX.invtsc [bit 8] x86 macOS itself relies on a fixed rate TSC for its own Mach absolute time timestamp mechanism, so there's no reason we can't enable this bit for gues= ts. When the feature is enabled, a migration blocker is installed. Signed-off-by: Phil Dennis-Jordan Reviewed-by: Roman Bolshakov Tested-by: Roman Bolshakov Message-ID: <20240605112556.43193-2-phil@philjordan.eu> Signed-off-by: Paolo Bonzini --- target/i386/hvf/hvf.c | 18 ++++++++++++++++++ target/i386/hvf/x86_cpuid.c | 4 ++++ 2 files changed, 22 insertions(+) diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c index e493452acb9..e6e916225bf 100644 --- a/target/i386/hvf/hvf.c +++ b/target/i386/hvf/hvf.c @@ -49,6 +49,8 @@ #include "qemu/osdep.h" #include "qemu/error-report.h" #include "qemu/memalign.h" +#include "qapi/error.h" +#include "migration/blocker.h" =20 #include "sysemu/hvf.h" #include "sysemu/hvf_int.h" @@ -74,6 +76,8 @@ #include "qemu/accel.h" #include "target/i386/cpu.h" =20 +static Error *invtsc_mig_blocker; + void vmx_update_tpr(CPUState *cpu) { /* TODO: need integrate APIC handling */ @@ -221,6 +225,8 @@ int hvf_arch_init_vcpu(CPUState *cpu) { X86CPU *x86cpu =3D X86_CPU(cpu); CPUX86State *env =3D &x86cpu->env; + Error *local_err =3D NULL; + int r; uint64_t reqCap; =20 init_emu(); @@ -238,6 +244,18 @@ int hvf_arch_init_vcpu(CPUState *cpu) } } =20 + if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) && + invtsc_mig_blocker =3D=3D NULL) { + error_setg(&invtsc_mig_blocker, + "State blocked by non-migratable CPU device (invtsc fla= g)"); + r =3D migrate_add_blocker(&invtsc_mig_blocker, &local_err); + if (r < 0) { + error_report_err(local_err); + return r; + } + } + + if (hv_vmx_read_capability(HV_VMX_CAP_PINBASED, &hvf_state->hvf_caps->vmx_cap_pinbased)) { abort(); diff --git a/target/i386/hvf/x86_cpuid.c b/target/i386/hvf/x86_cpuid.c index 9380b90496e..e56cd8411ba 100644 --- a/target/i386/hvf/x86_cpuid.c +++ b/target/i386/hvf/x86_cpuid.c @@ -146,6 +146,10 @@ uint32_t hvf_get_supported_cpuid(uint32_t func, uint32= _t idx, CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_OSVW | CPUID_EXT3_XO= P | CPUID_EXT3_FMA4 | CPUID_EXT3_TBM; break; + case 0x80000007: + edx &=3D CPUID_APM_INVTSC; + eax =3D ebx =3D ecx =3D 0; + break; default: return 0; } --=20 2.45.1