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Sat, 08 Jun 2024 01:34:23 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFA0saavFD8HanITQ106HeeMkOVMh3ZfY+DCsl9vfzPkMzrxwSi8ImQ6dT1Ctkj12C7Z7NEqA== X-Received: by 2002:a50:8d07:0:b0:57c:6338:328a with SMTP id 4fb4d7f45d1cf-57c6338371dmr1924770a12.30.1717835663183; Sat, 08 Jun 2024 01:34:23 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PULL 02/42] target/i386: fix implementation of ICEBP Date: Sat, 8 Jun 2024 10:33:35 +0200 Message-ID: <20240608083415.2769160-3-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240608083415.2769160-1-pbonzini@redhat.com> References: <20240608083415.2769160-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1717835732591100002 Content-Type: text/plain; charset="utf-8" ICEBP generates a trap-like exception, while gen_exception() produces a fault. Resurrect gen_update_eip_next() to implement the desired semantics. Reviewed-by: Richard Henderson Signed-off-by: Paolo Bonzini --- target/i386/helper.h | 1 + target/i386/tcg/helper-tcg.h | 12 +++++++++++- target/i386/tcg/excp_helper.c | 20 ++++++++++++++++++++ target/i386/tcg/translate.c | 13 +++++++++++++ target/i386/tcg/emit.c.inc | 5 ++++- 5 files changed, 49 insertions(+), 2 deletions(-) diff --git a/target/i386/helper.h b/target/i386/helper.h index a52a1bf0f21..8f291a5f66f 100644 --- a/target/i386/helper.h +++ b/target/i386/helper.h @@ -56,6 +56,7 @@ DEF_HELPER_2(sysret, void, env, int) DEF_HELPER_FLAGS_2(pause, TCG_CALL_NO_WG, noreturn, env, int) DEF_HELPER_FLAGS_3(raise_interrupt, TCG_CALL_NO_WG, noreturn, env, int, in= t) DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, int) +DEF_HELPER_FLAGS_1(icebp, TCG_CALL_NO_WG, noreturn, env) DEF_HELPER_3(boundw, void, env, tl, int) DEF_HELPER_3(boundl, void, env, tl, int) =20 diff --git a/target/i386/tcg/helper-tcg.h b/target/i386/tcg/helper-tcg.h index 85957943bf3..eb6a4926a43 100644 --- a/target/i386/tcg/helper-tcg.h +++ b/target/i386/tcg/helper-tcg.h @@ -111,7 +111,17 @@ int exception_has_error_code(int intno); /* smm_helper.c */ void do_smm_enter(X86CPU *cpu); =20 -/* bpt_helper.c */ +/* sysemu/bpt_helper.c */ bool check_hw_breakpoints(CPUX86State *env, bool force_dr6_update); =20 +/* + * Do the tasks usually performed by gen_eob(). Callers of this function + * should also handle TF as appropriate. + */ +static inline void do_end_instruction(CPUX86State *env) +{ + /* needed if sti is just before */ + env->hflags &=3D ~HF_INHIBIT_IRQ_MASK; + env->eflags &=3D ~HF_RF_MASK; +} #endif /* I386_HELPER_TCG_H */ diff --git a/target/i386/tcg/excp_helper.c b/target/i386/tcg/excp_helper.c index 65e37ae2a0c..72387aac24f 100644 --- a/target/i386/tcg/excp_helper.c +++ b/target/i386/tcg/excp_helper.c @@ -140,6 +140,26 @@ G_NORETURN void raise_exception_ra(CPUX86State *env, i= nt exception_index, raise_interrupt2(env, exception_index, 0, 0, 0, retaddr); } =20 +G_NORETURN void helper_icebp(CPUX86State *env) +{ + CPUState *cs =3D env_cpu(env); + + do_end_instruction(env); + + /* + * INT1 aka ICEBP generates a trap-like #DB, but it is pretty special. + * + * "Although the ICEBP instruction dispatches through IDT vector 1, + * that event is not interceptable by means of the #DB exception + * intercept". Instead there is a separate fault-like ICEBP intercept. + */ + cs->exception_index =3D EXCP01_DB; + env->error_code =3D 0; + env->exception_is_int =3D 0; + env->exception_next_eip =3D env->eip; + cpu_loop_exit(cs); +} + G_NORETURN void handle_unaligned_access(CPUX86State *env, vaddr vaddr, MMUAccessType access_type, uintptr_t retaddr) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index d438f8f76f7..77ed9c1db47 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -549,6 +549,19 @@ static inline void gen_op_st_rm_T0_A0(DisasContext *s,= int idx, int d) } } =20 +static void gen_update_eip_next(DisasContext *s) +{ + assert(s->pc_save !=3D -1); + if (tb_cflags(s->base.tb) & CF_PCREL) { + tcg_gen_addi_tl(cpu_eip, cpu_eip, s->pc - s->pc_save); + } else if (CODE64(s)) { + tcg_gen_movi_tl(cpu_eip, s->pc); + } else { + tcg_gen_movi_tl(cpu_eip, (uint32_t)(s->pc - s->cs_base)); + } + s->pc_save =3D s->pc; +} + static void gen_update_eip_cur(DisasContext *s) { assert(s->pc_save !=3D -1); diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc index e990141454b..36127d99943 100644 --- a/target/i386/tcg/emit.c.inc +++ b/target/i386/tcg/emit.c.inc @@ -1858,7 +1858,10 @@ static void gen_INT(DisasContext *s, CPUX86State *en= v, X86DecodedInsn *decode) =20 static void gen_INT1(DisasContext *s, CPUX86State *env, X86DecodedInsn *de= code) { - gen_exception(s, EXCP01_DB); + gen_update_cc_op(s); + gen_update_eip_next(s); + gen_helper_icebp(tcg_env); + s->base.is_jmp =3D DISAS_NORETURN; } =20 static void gen_INT3(DisasContext *s, CPUX86State *env, X86DecodedInsn *de= code) --=20 2.45.1