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Sat, 08 Jun 2024 01:35:54 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFhxrJpMz4UWUDt1yNq0Po5homi6nU35ddzjCl9/U7XRjPDOxNT2e+KLPzXVRWAkY9Bx9y0Gg== X-Received: by 2002:a50:9f25:0:b0:57a:6ed5:b327 with SMTP id 4fb4d7f45d1cf-57c508e1f3dmr3112974a12.12.1717835754597; Sat, 08 Jun 2024 01:35:54 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: John Allen , William Roche Subject: [PULL 38/42] i386: Fix MCE support for AMD hosts Date: Sat, 8 Jun 2024 10:34:11 +0200 Message-ID: <20240608083415.2769160-39-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240608083415.2769160-1-pbonzini@redhat.com> References: <20240608083415.2769160-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1717835860555100001 Content-Type: text/plain; charset="utf-8" From: John Allen For the most part, AMD hosts can use the same MCE injection code as Intel, = but there are instances where the qemu implementation is Intel specific. First,= MCE delivery works differently on AMD and does not support broadcast. Second, kvm_mce_inject generates MCEs that include a number of Intel specific status bits. Modify kvm_mce_inject to properly generate MCEs on AMD platforms. Reported-by: William Roche Signed-off-by: John Allen Message-ID: <20240603193622.47156-2-john.allen@amd.com> Signed-off-by: Paolo Bonzini --- target/i386/cpu.h | 2 ++ target/i386/helper.c | 4 ++++ target/i386/kvm/kvm.c | 39 +++++++++++++++++++++++++++++++-------- 3 files changed, 37 insertions(+), 8 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 29d799adfd6..e6d5d1b483c 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -377,6 +377,8 @@ typedef enum X86Seg { #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */ #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */ #define MCI_STATUS_AR (1ULL<<55) /* Action required */ +#define MCI_STATUS_DEFERRED (1ULL<<44) /* Deferred error */ +#define MCI_STATUS_POISON (1ULL<<43) /* Poisoned data consumed */ =20 /* MISC register defines */ #define MCM_ADDR_SEGOFF 0 /* segment offset */ diff --git a/target/i386/helper.c b/target/i386/helper.c index f9d1381f90b..01a268a30bb 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -91,6 +91,10 @@ int cpu_x86_support_mca_broadcast(CPUX86State *env) int family =3D 0; int model =3D 0; =20 + if (IS_AMD_CPU(env)) { + return 0; + } + cpu_x86_version(env, &family, &model); if ((family =3D=3D 6 && model >=3D 14) || family > 6) { return 1; diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index b5635209812..55a9e8a70cf 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -638,17 +638,40 @@ static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr,= int code) { CPUState *cs =3D CPU(cpu); CPUX86State *env =3D &cpu->env; - uint64_t status =3D MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN | - MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S; - uint64_t mcg_status =3D MCG_STATUS_MCIP; + uint64_t status =3D MCI_STATUS_VAL | MCI_STATUS_EN | MCI_STATUS_MISCV | + MCI_STATUS_ADDRV; + uint64_t mcg_status =3D MCG_STATUS_MCIP | MCG_STATUS_RIPV; int flags =3D 0; =20 - if (code =3D=3D BUS_MCEERR_AR) { - status |=3D MCI_STATUS_AR | 0x134; - mcg_status |=3D MCG_STATUS_RIPV | MCG_STATUS_EIPV; + if (!IS_AMD_CPU(env)) { + status |=3D MCI_STATUS_S | MCI_STATUS_UC; + if (code =3D=3D BUS_MCEERR_AR) { + status |=3D MCI_STATUS_AR | 0x134; + mcg_status |=3D MCG_STATUS_EIPV; + } else { + status |=3D 0xc0; + } } else { - status |=3D 0xc0; - mcg_status |=3D MCG_STATUS_RIPV; + if (code =3D=3D BUS_MCEERR_AR) { + status |=3D MCI_STATUS_UC | MCI_STATUS_POISON; + mcg_status |=3D MCG_STATUS_EIPV; + } else { + /* Setting the POISON bit for deferred errors indicates to the + * guest kernel that the address provided by the MCE is valid + * and usable which will ensure that the guest kernel will send + * a SIGBUS_AO signal to the guest process. This allows for + * more desirable behavior in the case that the guest process + * with poisoned memory has set the MCE_KILL_EARLY prctl flag + * which indicates that the process would prefer to handle or + * shutdown due to the poisoned memory condition before the + * memory has been accessed. + * + * While the POISON bit would not be set in a deferred error + * sent from hardware, the bit is not meaningful for deferred + * errors and can be reused in this scenario. + */ + status |=3D MCI_STATUS_DEFERRED | MCI_STATUS_POISON; + } } =20 flags =3D cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : = 0; --=20 2.45.1