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([2a01:e0a:999:a3a0:45f5:4d94:4aa8:def4]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-36077536f78sm13747059f8f.7.2024.06.18.04.27.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Jun 2024 04:27:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1718710041; x=1719314841; darn=nongnu.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=RENz7JQaP3Z2DOpOHwzXYz8SHC4pTV+PRNaAMchOSfk=; b=kj4Vhmj74j8I+6I0wz86xS5UN7OSNLNKWE7DoigBWAchsqdgp4CY2ge5oEWB5srH0t j4GTxqtDF7Anb8uvOUIXGvi5v1jbZWqCE8VQ5279sBqi7pDeDrrMgB9/b7fSGfubUwe1 IWkbTm/NrduAuHRgl8cuRCxyIfbw7K1MujMNw/BCDTKhsVeLMuV3JJ40PYDI/JAZDiAb OReszrFRj3rTqCLjIUFAw8NGMW2vBsYRMoFncJyv0YjuknZwB6fEDxsGhKtjhSnQ/+OB NK6TkzyeOBmn9LFDvpB1bvo1NvN5+36Z4Z5tGzAl7BLvmvtTJFsDleY1QrsjPB4qH/uL 23Yg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1718710041; x=1719314841; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=RENz7JQaP3Z2DOpOHwzXYz8SHC4pTV+PRNaAMchOSfk=; b=TxsUX2iWazJYKO3QLFO2kUfT7LVj77wIrDWlS6v04xX0KFfD7H191ZVeuM81T5xUqR VjhLeguL7vEqBQYFe87oajmT0Mu+Lh2hhXMQq0ugh9KDrIxLvxkj29wfW4A6beILE6rN Z5S5/wq4sF3YswkjaGNm4qVqkjO3d5fIsO6TwZfRoN4P+WIz95FcH9akhHocjlEZ0zes owTm7YCBYFOSwM6exeBXP0RmbLj3aGFyHGC2SDCN8D8LbTKF03bwo+FbPDGIwkOeP0k2 YzZgxs2bm717lUGY2ZsjZ+ZzIbc/mxR8MqFkq9sCoJxyz+D0ncFv6FSYSht+xyuLs5+G 5tjA== X-Forwarded-Encrypted: i=1; AJvYcCUkFEvdc3ebivDUdXqv0lHQqitODLXXWfmyy93kMhipON/wyi/y6yaJTj0M4OCT8FULUtd9siH/xfGbhdEH8Zi7dbkjA6E= X-Gm-Message-State: AOJu0Yy1kmWqys7P3rRMGOayNBTvp0soMmlvA/TxhjVQQjMwOmQY/jha /sJMRB+o4Hc5JCKy33SKWBjVwKFPNKHMvOMVLYzaQ2sGd//rn7pD+rGKC1Ya5bs= X-Google-Smtp-Source: AGHT+IGQUR+ItdVrGYzNnFg9ogR/DwQcqbsRLzOvVokKC/gCBXZ6gXTycVfOl9MRlib76ORUT1ThQA== X-Received: by 2002:a05:6000:1844:b0:35f:2584:76e9 with SMTP id ffacd0b85a97d-3607a76aa50mr9707645f8f.2.1718710040861; Tue, 18 Jun 2024 04:27:20 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , qemu-devel@nongnu.org, Atish Patra Subject: [PATCH v2] target/riscv: fix instructions count handling in icount mode Date: Tue, 18 Jun 2024 13:26:45 +0200 Message-ID: <20240618112649.76683-1-cleger@rivosinc.com> X-Mailer: git-send-email 2.45.2 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=cleger@rivosinc.com; helo=mail-wm1-x331.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1718710091760100003 When icount is enabled, rather than returning the virtual CPU time, we should return the instruction count itself. Add an instructions bool parameter to get_ticks() to correctly return icount_get_raw() when icount_enabled() =3D=3D 1 and instruction count is queried. This will modify the existing behavior which was returning an instructions count close to the number of cycles (CPI ~=3D 1). Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Atish Patra --- v2: - Apply checkpatch and fixed missing braces --- target/riscv/csr.c | 30 +++++++++++++++++------------- 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 58ef7079dc..b8915e32a2 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -762,14 +762,18 @@ static RISCVException write_vcsr(CPURISCVState *env, = int csrno, } =20 /* User Timers and Counters */ -static target_ulong get_ticks(bool shift) +static target_ulong get_ticks(bool shift, bool instructions) { int64_t val; target_ulong result; =20 #if !defined(CONFIG_USER_ONLY) if (icount_enabled()) { - val =3D icount_get(); + if (instructions) { + val =3D icount_get_raw(); + } else { + val =3D icount_get(); + } } else { val =3D cpu_get_host_ticks(); } @@ -804,14 +808,14 @@ static RISCVException read_timeh(CPURISCVState *env, = int csrno, static RISCVException read_hpmcounter(CPURISCVState *env, int csrno, target_ulong *val) { - *val =3D get_ticks(false); + *val =3D get_ticks(false, (csrno =3D=3D CSR_INSTRET)); return RISCV_EXCP_NONE; } =20 static RISCVException read_hpmcounterh(CPURISCVState *env, int csrno, target_ulong *val) { - *val =3D get_ticks(true); + *val =3D get_ticks(true, (csrno =3D=3D CSR_INSTRETH)); return RISCV_EXCP_NONE; } =20 @@ -875,11 +879,11 @@ static RISCVException write_mhpmcounter(CPURISCVState= *env, int csrno, int ctr_idx =3D csrno - CSR_MCYCLE; PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; uint64_t mhpmctr_val =3D val; + bool instr =3D riscv_pmu_ctr_monitor_instructions(env, ctr_idx); =20 counter->mhpmcounter_val =3D val; - if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || - riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { - counter->mhpmcounter_prev =3D get_ticks(false); + if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || instr) { + counter->mhpmcounter_prev =3D get_ticks(false, instr); if (ctr_idx > 2) { if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { mhpmctr_val =3D mhpmctr_val | @@ -902,12 +906,12 @@ static RISCVException write_mhpmcounterh(CPURISCVStat= e *env, int csrno, PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; uint64_t mhpmctr_val =3D counter->mhpmcounter_val; uint64_t mhpmctrh_val =3D val; + bool instr =3D riscv_pmu_ctr_monitor_instructions(env, ctr_idx); =20 counter->mhpmcounterh_val =3D val; mhpmctr_val =3D mhpmctr_val | (mhpmctrh_val << 32); - if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || - riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { - counter->mhpmcounterh_prev =3D get_ticks(true); + if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || instr) { + counter->mhpmcounterh_prev =3D get_ticks(true, instr); if (ctr_idx > 2) { riscv_pmu_setup_timer(env, mhpmctr_val, ctr_idx); } @@ -926,6 +930,7 @@ static RISCVException riscv_pmu_read_ctr(CPURISCVState = *env, target_ulong *val, counter->mhpmcounter_prev; target_ulong ctr_val =3D upper_half ? counter->mhpmcounterh_val : counter->mhpmcounter_val; + bool instr =3D riscv_pmu_ctr_monitor_instructions(env, ctr_idx); =20 if (get_field(env->mcountinhibit, BIT(ctr_idx))) { /* @@ -946,9 +951,8 @@ static RISCVException riscv_pmu_read_ctr(CPURISCVState = *env, target_ulong *val, * The kernel computes the perf delta by subtracting the current value= from * the value it initialized previously (ctr_val). */ - if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || - riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { - *val =3D get_ticks(upper_half) - ctr_prev + ctr_val; + if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || instr) { + *val =3D get_ticks(upper_half, instr) - ctr_prev + ctr_val; } else { *val =3D ctr_val; } --=20 2.45.2