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Thu, 20 Jun 2024 02:54:35 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGZTVdp7EDyHKEdoVsQy5stamWPmbMxNbWR5yganNv2dmL6fPZ71scaEKw7rFG0SXHjfMgdLg== X-Received: by 2002:a50:cc93:0:b0:57c:c712:a3c7 with SMTP id 4fb4d7f45d1cf-57d07ee6e85mr2917805a12.36.1718877275106; Thu, 20 Jun 2024 02:54:35 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PATCH 05/10] target/i386: decode address before going back to translate.c Date: Thu, 20 Jun 2024 11:54:14 +0200 Message-ID: <20240620095419.386958-6-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240620095419.386958-1-pbonzini@redhat.com> References: <20240620095419.386958-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.144, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1718877447850100003 Content-Type: text/plain; charset="utf-8" There are now relatively few unconverted opcodes in translate.c (there are 13 of them including 8 for x87), and all of them have the same format with a mod/rm byte and no immediate. A good next step is to remove the early bail out to disas_insn_x87/disas_insn_old, instead giving these legacy translator functions the same prototype as the other gen_* functions. To do this, the X86DecodeInsn can be passed down to the places that used to fetch address bytes from the instruction stream. To make sure that everything is done cleanly, the CPUX86State* argument is removed. As part of the unification, the gen_lea_modrm() name is now free, so rename gen_load_ea() to gen_lea_modrm(). This is as good a name and it makes the changes to translate.c easier to review. Reviewed-by: Richard Henderson Signed-off-by: Paolo Bonzini --- target/i386/tcg/decode-new.h | 14 ++- target/i386/tcg/translate.c | 152 +++++++++++++------------------ target/i386/tcg/decode-new.c.inc | 53 ++++++----- target/i386/tcg/emit.c.inc | 2 +- 4 files changed, 103 insertions(+), 118 deletions(-) diff --git a/target/i386/tcg/decode-new.h b/target/i386/tcg/decode-new.h index e4cdf5e3c4f..bebc77bd54b 100644 --- a/target/i386/tcg/decode-new.h +++ b/target/i386/tcg/decode-new.h @@ -264,12 +264,13 @@ typedef enum X86VEXSpecial { =20 typedef struct X86OpEntry X86OpEntry; typedef struct X86DecodedInsn X86DecodedInsn; +struct DisasContext; =20 /* Decode function for multibyte opcodes. */ -typedef void (*X86DecodeFunc)(DisasContext *s, CPUX86State *env, X86OpEntr= y *entry, uint8_t *b); +typedef void (*X86DecodeFunc)(struct DisasContext *s, CPUX86State *env, X8= 6OpEntry *entry, uint8_t *b); =20 /* Code generation function. */ -typedef void (*X86GenFunc)(DisasContext *s, X86DecodedInsn *decode); +typedef void (*X86GenFunc)(struct DisasContext *s, X86DecodedInsn *decode); =20 struct X86OpEntry { /* Based on the is_decode flags. */ @@ -316,6 +317,14 @@ typedef struct X86DecodedOp { }; } X86DecodedOp; =20 +typedef struct AddressParts { + int def_seg; + int base; + int index; + int scale; + target_long disp; +} AddressParts; + struct X86DecodedInsn { X86OpEntry e; X86DecodedOp op[3]; @@ -333,3 +342,4 @@ struct X86DecodedInsn { uint8_t b; }; =20 +static void gen_lea_modrm(struct DisasContext *s, X86DecodedInsn *decode); diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 08db40681fa..1d845ff66bb 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -29,6 +29,7 @@ #include "exec/helper-proto.h" #include "exec/helper-gen.h" #include "helper-tcg.h" +#include "decode-new.h" =20 #include "exec/log.h" =20 @@ -1529,14 +1530,6 @@ static inline uint64_t x86_ldq_code(CPUX86State *env= , DisasContext *s) =20 /* Decompose an address. */ =20 -typedef struct AddressParts { - int def_seg; - int base; - int index; - int scale; - target_long disp; -} AddressParts; - static AddressParts gen_lea_modrm_0(CPUX86State *env, DisasContext *s, int modrm) { @@ -1695,24 +1688,11 @@ static TCGv gen_lea_modrm_1(DisasContext *s, Addres= sParts a, bool is_vsib) return ea; } =20 -static void gen_lea_modrm(CPUX86State *env, DisasContext *s, int modrm) -{ - AddressParts a =3D gen_lea_modrm_0(env, s, modrm); - TCGv ea =3D gen_lea_modrm_1(s, a, false); - gen_lea_v_seg(s, ea, a.def_seg, s->override); -} - -static void gen_nop_modrm(CPUX86State *env, DisasContext *s, int modrm) -{ - (void)gen_lea_modrm_0(env, s, modrm); -} - /* Used for BNDCL, BNDCU, BNDCN. */ -static void gen_bndck(CPUX86State *env, DisasContext *s, int modrm, +static void gen_bndck(DisasContext *s, X86DecodedInsn *decode, TCGCond cond, TCGv_i64 bndv) { - AddressParts a =3D gen_lea_modrm_0(env, s, modrm); - TCGv ea =3D gen_lea_modrm_1(s, a, false); + TCGv ea =3D gen_lea_modrm_1(s, decode->mem, false); =20 tcg_gen_extu_tl_i64(s->tmp1_i64, ea); if (!CODE64(s)) { @@ -1724,8 +1704,9 @@ static void gen_bndck(CPUX86State *env, DisasContext = *s, int modrm, } =20 /* generate modrm load of memory or register. */ -static void gen_ld_modrm(CPUX86State *env, DisasContext *s, int modrm, Mem= Op ot) +static void gen_ld_modrm(DisasContext *s, X86DecodedInsn *decode, MemOp ot) { + int modrm =3D s->modrm; int mod, rm; =20 mod =3D (modrm >> 6) & 3; @@ -1733,14 +1714,15 @@ static void gen_ld_modrm(CPUX86State *env, DisasCon= text *s, int modrm, MemOp ot) if (mod =3D=3D 3) { gen_op_mov_v_reg(s, ot, s->T0, rm); } else { - gen_lea_modrm(env, s, modrm); + gen_lea_modrm(s, decode); gen_op_ld_v(s, ot, s->T0, s->A0); } } =20 /* generate modrm store of memory or register. */ -static void gen_st_modrm(CPUX86State *env, DisasContext *s, int modrm, Mem= Op ot) +static void gen_st_modrm(DisasContext *s, X86DecodedInsn *decode, MemOp ot) { + int modrm =3D s->modrm; int mod, rm; =20 mod =3D (modrm >> 6) & 3; @@ -1748,7 +1730,7 @@ static void gen_st_modrm(CPUX86State *env, DisasConte= xt *s, int modrm, MemOp ot) if (mod =3D=3D 3) { gen_op_mov_reg_v(s, ot, rm, s->T0); } else { - gen_lea_modrm(env, s, modrm); + gen_lea_modrm(s, decode); gen_op_st_v(s, ot, s->T0, s->A0); } } @@ -2316,12 +2298,12 @@ static void gen_sty_env_A0(DisasContext *s, int off= set, bool align) tcg_gen_qemu_st_i128(t, s->tmp0, mem_index, mop); } =20 -static void gen_cmpxchg8b(DisasContext *s, CPUX86State *env, int modrm) +static void gen_cmpxchg8b(DisasContext *s, X86DecodedInsn *decode) { TCGv_i64 cmp, val, old; TCGv Z; =20 - gen_lea_modrm(env, s, modrm); + gen_lea_modrm(s, decode); =20 cmp =3D tcg_temp_new_i64(); val =3D tcg_temp_new_i64(); @@ -2370,13 +2352,13 @@ static void gen_cmpxchg8b(DisasContext *s, CPUX86St= ate *env, int modrm) } =20 #ifdef TARGET_X86_64 -static void gen_cmpxchg16b(DisasContext *s, CPUX86State *env, int modrm) +static void gen_cmpxchg16b(DisasContext *s, X86DecodedInsn *decode) { MemOp mop =3D MO_TE | MO_128 | MO_ALIGN; TCGv_i64 t0, t1; TCGv_i128 cmp, val; =20 - gen_lea_modrm(env, s, modrm); + gen_lea_modrm(s, decode); =20 cmp =3D tcg_temp_new_i128(); val =3D tcg_temp_new_i128(); @@ -2414,31 +2396,32 @@ static void gen_cmpxchg16b(DisasContext *s, CPUX86S= tate *env, int modrm) } #endif =20 -static bool disas_insn_x87(DisasContext *s, CPUState *cpu, int b) +#include "emit.c.inc" + +static void gen_x87(DisasContext *s, X86DecodedInsn *decode) { - CPUX86State *env =3D cpu_env(cpu); bool update_fip =3D true; - int modrm, mod, rm, op; + int b =3D decode->b; + int modrm =3D s->modrm; + int mod, rm, op; =20 if (s->flags & (HF_EM_MASK | HF_TS_MASK)) { /* if CR0.EM or CR0.TS are set, generate an FPU exception */ /* XXX: what to do if illegal op ? */ gen_exception(s, EXCP07_PREX); - return true; + return; } - modrm =3D x86_ldub_code(env, s); mod =3D (modrm >> 6) & 3; rm =3D modrm & 7; op =3D ((b & 7) << 3) | ((modrm >> 3) & 7); if (mod !=3D 3) { /* memory op */ - AddressParts a =3D gen_lea_modrm_0(env, s, modrm); - TCGv ea =3D gen_lea_modrm_1(s, a, false); + TCGv ea =3D gen_lea_modrm_1(s, decode->mem, false); TCGv last_addr =3D tcg_temp_new(); bool update_fdp =3D true; =20 tcg_gen_mov_tl(last_addr, ea); - gen_lea_v_seg(s, ea, a.def_seg, s->override); + gen_lea_v_seg(s, ea, decode->mem.def_seg, s->override); =20 switch (op) { case 0x00 ... 0x07: /* fxxxs */ @@ -2628,11 +2611,11 @@ static bool disas_insn_x87(DisasContext *s, CPUStat= e *cpu, int b) gen_helper_fpop(tcg_env); break; default: - return false; + goto illegal_op; } =20 if (update_fdp) { - int last_seg =3D s->override >=3D 0 ? s->override : a.def_seg; + int last_seg =3D s->override >=3D 0 ? s->override : decode->me= m.def_seg; =20 tcg_gen_ld_i32(s->tmp2_i32, tcg_env, offsetof(CPUX86State, @@ -2669,7 +2652,7 @@ static bool disas_insn_x87(DisasContext *s, CPUState = *cpu, int b) update_fip =3D false; break; default: - return false; + goto illegal_op; } break; case 0x0c: /* grp d9/4 */ @@ -2688,7 +2671,7 @@ static bool disas_insn_x87(DisasContext *s, CPUState = *cpu, int b) gen_helper_fxam_ST0(tcg_env); break; default: - return false; + goto illegal_op; } break; case 0x0d: /* grp d9/5 */ @@ -2723,7 +2706,7 @@ static bool disas_insn_x87(DisasContext *s, CPUState = *cpu, int b) gen_helper_fldz_ST0(tcg_env); break; default: - return false; + goto illegal_op; } } break; @@ -2825,7 +2808,7 @@ static bool disas_insn_x87(DisasContext *s, CPUState = *cpu, int b) gen_helper_fpop(tcg_env); break; default: - return false; + goto illegal_op; } break; case 0x1c: @@ -2845,7 +2828,7 @@ static bool disas_insn_x87(DisasContext *s, CPUState = *cpu, int b) case 4: /* fsetpm (287 only, just do nop here) */ break; default: - return false; + goto illegal_op; } break; case 0x1d: /* fucomi */ @@ -2897,7 +2880,7 @@ static bool disas_insn_x87(DisasContext *s, CPUState = *cpu, int b) gen_helper_fpop(tcg_env); break; default: - return false; + goto illegal_op; } break; case 0x38: /* ffreep sti, undocumented op */ @@ -2912,7 +2895,7 @@ static bool disas_insn_x87(DisasContext *s, CPUState = *cpu, int b) gen_op_mov_reg_v(s, MO_16, R_EAX, s->T0); break; default: - return false; + goto illegal_op; } break; case 0x3d: /* fucomip */ @@ -2959,7 +2942,7 @@ static bool disas_insn_x87(DisasContext *s, CPUState = *cpu, int b) } break; default: - return false; + goto illegal_op; } } =20 @@ -2971,25 +2954,24 @@ static bool disas_insn_x87(DisasContext *s, CPUStat= e *cpu, int b) tcg_gen_st_tl(eip_cur_tl(s), tcg_env, offsetof(CPUX86State, fpip)); } - return true; + return; =20 illegal_op: gen_illegal_opcode(s); - return true; } =20 -static void disas_insn_old(DisasContext *s, CPUState *cpu, int b) +static void gen_multi0F(DisasContext *s, X86DecodedInsn *decode) { - CPUX86State *env =3D cpu_env(cpu); int prefixes =3D s->prefix; MemOp dflag =3D s->dflag; + int b =3D decode->b + 0x100; + int modrm =3D s->modrm; MemOp ot; - int modrm, reg, rm, mod, op; + int reg, rm, mod, op; =20 /* now check op code */ switch (b) { case 0x1c7: /* cmpxchg8b */ - modrm =3D x86_ldub_code(env, s); mod =3D (modrm >> 6) & 3; switch ((modrm >> 3) & 7) { case 1: /* CMPXCHG8, CMPXCHG16 */ @@ -3001,14 +2983,14 @@ static void disas_insn_old(DisasContext *s, CPUStat= e *cpu, int b) if (!(s->cpuid_ext_features & CPUID_EXT_CX16)) { goto illegal_op; } - gen_cmpxchg16b(s, env, modrm); + gen_cmpxchg16b(s, decode); break; } #endif if (!(s->cpuid_features & CPUID_CX8)) { goto illegal_op; } - gen_cmpxchg8b(s, env, modrm); + gen_cmpxchg8b(s, decode); break; =20 case 7: /* RDSEED, RDPID with f3 prefix */ @@ -3051,7 +3033,6 @@ static void disas_insn_old(DisasContext *s, CPUState = *cpu, int b) break; =20 case 0x100: - modrm =3D x86_ldub_code(env, s); mod =3D (modrm >> 6) & 3; op =3D (modrm >> 3) & 7; switch(op) { @@ -3065,14 +3046,14 @@ static void disas_insn_old(DisasContext *s, CPUStat= e *cpu, int b) tcg_gen_ld32u_tl(s->T0, tcg_env, offsetof(CPUX86State, ldt.selector)); ot =3D mod =3D=3D 3 ? dflag : MO_16; - gen_st_modrm(env, s, modrm, ot); + gen_st_modrm(s, decode, ot); break; case 2: /* lldt */ if (!PE(s) || VM86(s)) goto illegal_op; if (check_cpl0(s)) { gen_svm_check_intercept(s, SVM_EXIT_LDTR_WRITE); - gen_ld_modrm(env, s, modrm, MO_16); + gen_ld_modrm(s, decode, MO_16); tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); gen_helper_lldt(tcg_env, s->tmp2_i32); } @@ -3087,14 +3068,14 @@ static void disas_insn_old(DisasContext *s, CPUStat= e *cpu, int b) tcg_gen_ld32u_tl(s->T0, tcg_env, offsetof(CPUX86State, tr.selector)); ot =3D mod =3D=3D 3 ? dflag : MO_16; - gen_st_modrm(env, s, modrm, ot); + gen_st_modrm(s, decode, ot); break; case 3: /* ltr */ if (!PE(s) || VM86(s)) goto illegal_op; if (check_cpl0(s)) { gen_svm_check_intercept(s, SVM_EXIT_TR_WRITE); - gen_ld_modrm(env, s, modrm, MO_16); + gen_ld_modrm(s, decode, MO_16); tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); gen_helper_ltr(tcg_env, s->tmp2_i32); } @@ -3103,7 +3084,7 @@ static void disas_insn_old(DisasContext *s, CPUState = *cpu, int b) case 5: /* verw */ if (!PE(s) || VM86(s)) goto illegal_op; - gen_ld_modrm(env, s, modrm, MO_16); + gen_ld_modrm(s, decode, MO_16); gen_update_cc_op(s); if (op =3D=3D 4) { gen_helper_verr(tcg_env, s->T0); @@ -3113,19 +3094,18 @@ static void disas_insn_old(DisasContext *s, CPUStat= e *cpu, int b) assume_cc_op(s, CC_OP_EFLAGS); break; default: - goto unknown_op; + goto illegal_op; } break; =20 case 0x101: - modrm =3D x86_ldub_code(env, s); switch (modrm) { CASE_MODRM_MEM_OP(0): /* sgdt */ if (s->flags & HF_UMIP_MASK && !check_cpl0(s)) { break; } gen_svm_check_intercept(s, SVM_EXIT_GDTR_READ); - gen_lea_modrm(env, s, modrm); + gen_lea_modrm(s, decode); tcg_gen_ld32u_tl(s->T0, tcg_env, offsetof(CPUX86State, gdt.limit)); gen_op_st_v(s, MO_16, s->T0, s->A0); @@ -3181,7 +3161,7 @@ static void disas_insn_old(DisasContext *s, CPUState = *cpu, int b) break; } gen_svm_check_intercept(s, SVM_EXIT_IDTR_READ); - gen_lea_modrm(env, s, modrm); + gen_lea_modrm(s, decode); tcg_gen_ld32u_tl(s->T0, tcg_env, offsetof(CPUX86State, idt.lim= it)); gen_op_st_v(s, MO_16, s->T0, s->A0); gen_add_A0_im(s, 2); @@ -3331,7 +3311,7 @@ static void disas_insn_old(DisasContext *s, CPUState = *cpu, int b) break; } gen_svm_check_intercept(s, SVM_EXIT_GDTR_WRITE); - gen_lea_modrm(env, s, modrm); + gen_lea_modrm(s, decode); gen_op_ld_v(s, MO_16, s->T1, s->A0); gen_add_A0_im(s, 2); gen_op_ld_v(s, CODE64(s) + MO_32, s->T0, s->A0); @@ -3347,7 +3327,7 @@ static void disas_insn_old(DisasContext *s, CPUState = *cpu, int b) break; } gen_svm_check_intercept(s, SVM_EXIT_IDTR_WRITE); - gen_lea_modrm(env, s, modrm); + gen_lea_modrm(s, decode); gen_op_ld_v(s, MO_16, s->T1, s->A0); gen_add_A0_im(s, 2); gen_op_ld_v(s, CODE64(s) + MO_32, s->T0, s->A0); @@ -3371,7 +3351,7 @@ static void disas_insn_old(DisasContext *s, CPUState = *cpu, int b) */ mod =3D (modrm >> 6) & 3; ot =3D (mod !=3D 3 ? MO_16 : s->dflag); - gen_st_modrm(env, s, modrm, ot); + gen_st_modrm(s, decode, ot); break; case 0xee: /* rdpkru */ if (s->prefix & (PREFIX_LOCK | PREFIX_DATA @@ -3398,7 +3378,7 @@ static void disas_insn_old(DisasContext *s, CPUState = *cpu, int b) break; } gen_svm_check_intercept(s, SVM_EXIT_WRITE_CR0); - gen_ld_modrm(env, s, modrm, MO_16); + gen_ld_modrm(s, decode, MO_16); /* * Only the 4 lower bits of CR0 are modified. * PE cannot be set to zero if already set to one. @@ -3416,7 +3396,7 @@ static void disas_insn_old(DisasContext *s, CPUState = *cpu, int b) break; } gen_svm_check_intercept(s, SVM_EXIT_INVLPG); - gen_lea_modrm(env, s, modrm); + gen_lea_modrm(s, decode); gen_helper_flush_page(tcg_env, s->A0); s->base.is_jmp =3D DISAS_EOB_NEXT; break; @@ -3449,12 +3429,11 @@ static void disas_insn_old(DisasContext *s, CPUStat= e *cpu, int b) break; =20 default: - goto unknown_op; + goto illegal_op; } break; =20 case 0x11a: - modrm =3D x86_ldub_code(env, s); if (s->flags & HF_MPX_EN_MASK) { mod =3D (modrm >> 6) & 3; reg =3D ((modrm >> 3) & 7) | REX_R(s); @@ -3465,7 +3444,7 @@ static void disas_insn_old(DisasContext *s, CPUState = *cpu, int b) || s->aflag =3D=3D MO_16) { goto illegal_op; } - gen_bndck(env, s, modrm, TCG_COND_LTU, cpu_bndl[reg]); + gen_bndck(s, decode, TCG_COND_LTU, cpu_bndl[reg]); } else if (prefixes & PREFIX_REPNZ) { /* bndcu */ if (reg >=3D 4 @@ -3475,7 +3454,7 @@ static void disas_insn_old(DisasContext *s, CPUState = *cpu, int b) } TCGv_i64 notu =3D tcg_temp_new_i64(); tcg_gen_not_i64(notu, cpu_bndu[reg]); - gen_bndck(env, s, modrm, TCG_COND_GTU, notu); + gen_bndck(s, decode, TCG_COND_GTU, notu); } else if (prefixes & PREFIX_DATA) { /* bndmov -- from reg/mem */ if (reg >=3D 4 || s->aflag =3D=3D MO_16) { @@ -3491,7 +3470,7 @@ static void disas_insn_old(DisasContext *s, CPUState = *cpu, int b) tcg_gen_mov_i64(cpu_bndu[reg], cpu_bndu[reg2]); } } else { - gen_lea_modrm(env, s, modrm); + gen_lea_modrm(s, decode); if (CODE64(s)) { tcg_gen_qemu_ld_i64(cpu_bndl[reg], s->A0, s->mem_index, MO_LEUQ); @@ -3510,7 +3489,7 @@ static void disas_insn_old(DisasContext *s, CPUState = *cpu, int b) } } else if (mod !=3D 3) { /* bndldx */ - AddressParts a =3D gen_lea_modrm_0(env, s, modrm); + AddressParts a =3D decode->mem; if (reg >=3D 4 || (prefixes & PREFIX_LOCK) || s->aflag =3D=3D MO_16 @@ -3540,10 +3519,8 @@ static void disas_insn_old(DisasContext *s, CPUState= *cpu, int b) gen_set_hflag(s, HF_MPX_IU_MASK); } } - gen_nop_modrm(env, s, modrm); break; case 0x11b: - modrm =3D x86_ldub_code(env, s); if (s->flags & HF_MPX_EN_MASK) { mod =3D (modrm >> 6) & 3; reg =3D ((modrm >> 3) & 7) | REX_R(s); @@ -3554,7 +3531,7 @@ static void disas_insn_old(DisasContext *s, CPUState = *cpu, int b) || s->aflag =3D=3D MO_16) { goto illegal_op; } - AddressParts a =3D gen_lea_modrm_0(env, s, modrm); + AddressParts a =3D decode->mem; if (a.base >=3D 0) { tcg_gen_extu_tl_i64(cpu_bndl[reg], cpu_regs[a.base]); if (!CODE64(s)) { @@ -3567,7 +3544,7 @@ static void disas_insn_old(DisasContext *s, CPUState = *cpu, int b) /* rip-relative generates #ud */ goto illegal_op; } - tcg_gen_not_tl(s->A0, gen_lea_modrm_1(s, a, false)); + tcg_gen_not_tl(s->A0, gen_lea_modrm_1(s, decode->mem, fals= e)); if (!CODE64(s)) { tcg_gen_ext32u_tl(s->A0, s->A0); } @@ -3582,7 +3559,7 @@ static void disas_insn_old(DisasContext *s, CPUState = *cpu, int b) || s->aflag =3D=3D MO_16) { goto illegal_op; } - gen_bndck(env, s, modrm, TCG_COND_GTU, cpu_bndu[reg]); + gen_bndck(s, decode, TCG_COND_GTU, cpu_bndu[reg]); } else if (prefixes & PREFIX_DATA) { /* bndmov -- to reg/mem */ if (reg >=3D 4 || s->aflag =3D=3D MO_16) { @@ -3598,7 +3575,7 @@ static void disas_insn_old(DisasContext *s, CPUState = *cpu, int b) tcg_gen_mov_i64(cpu_bndu[reg2], cpu_bndu[reg]); } } else { - gen_lea_modrm(env, s, modrm); + gen_lea_modrm(s, decode); if (CODE64(s)) { tcg_gen_qemu_st_i64(cpu_bndl[reg], s->A0, s->mem_index, MO_LEUQ); @@ -3615,7 +3592,7 @@ static void disas_insn_old(DisasContext *s, CPUState = *cpu, int b) } } else if (mod !=3D 3) { /* bndstx */ - AddressParts a =3D gen_lea_modrm_0(env, s, modrm); + AddressParts a =3D decode->mem; if (reg >=3D 4 || (prefixes & PREFIX_LOCK) || s->aflag =3D=3D MO_16 @@ -3642,7 +3619,6 @@ static void disas_insn_old(DisasContext *s, CPUState = *cpu, int b) } } } - gen_nop_modrm(env, s, modrm); break; default: g_assert_not_reached(); @@ -3651,12 +3627,8 @@ static void disas_insn_old(DisasContext *s, CPUState= *cpu, int b) illegal_op: gen_illegal_opcode(s); return; - unknown_op: - gen_unknown_opcode(env, s); } =20 -#include "decode-new.h" -#include "emit.c.inc" #include "decode-new.c.inc" =20 void tcg_x86_init(void) diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.= c.inc index 33ffcf092ec..45f4aed4611 100644 --- a/target/i386/tcg/decode-new.c.inc +++ b/target/i386/tcg/decode-new.c.inc @@ -1092,6 +1092,8 @@ static void decode_MOV_CR_DR(DisasContext *s, CPUX86S= tate *env, X86OpEntry *entr } =20 static const X86OpEntry opcodes_0F[256] =3D { + [0x00] =3D X86_OP_ENTRY1(multi0F, nop,v, nolea), /*= unconverted */ + [0x01] =3D X86_OP_ENTRY1(multi0F, nop,v, nolea), /*= unconverted */ [0x02] =3D X86_OP_ENTRYwr(LAR, G,v, E,w, chk(prot)), [0x03] =3D X86_OP_ENTRYwr(LSL, G,v, E,w, chk(prot)), [0x05] =3D X86_OP_ENTRY0(SYSCALL, chk(o64_in= tel)), @@ -1201,6 +1203,7 @@ static const X86OpEntry opcodes_0F[256] =3D { [0xc4] =3D X86_OP_ENTRY4(PINSRW, V,dq,H,dq,E,w, vex5 mmx p_0= 0_66), [0xc5] =3D X86_OP_ENTRY3(PEXTRW, G,d, U,dq,I,b, vex5 mmx p_0= 0_66), [0xc6] =3D X86_OP_ENTRY4(VSHUF, V,x, H,x, W,x, vex4 p_00_66= ), + [0xc7] =3D X86_OP_ENTRY1(multi0F, nop,v, nolea), /* u= nconverted */ =20 [0xd0] =3D X86_OP_ENTRY3(VADDSUB, V,x, H,x, W,x, vex2 cpuid(S= SE3) p_66_f2), [0xd1] =3D X86_OP_ENTRY3(PSRLW_r, V,x, H,x, W,x, vex4 mmx avx= 2_256 p_00_66), @@ -1243,6 +1246,8 @@ static const X86OpEntry opcodes_0F[256] =3D { =20 [0x18] =3D X86_OP_ENTRY1(NOP, nop,v), /* prefetch/reserved NOP */ [0x19] =3D X86_OP_ENTRY1(NOP, nop,v), /* reserved NOP */ + [0x1a] =3D X86_OP_ENTRY1(multi0F, nop,v, nolea), /* unconverted MPX */ + [0x1b] =3D X86_OP_ENTRY1(multi0F, nop,v, nolea), /* unconverted MPX */ [0x1c] =3D X86_OP_ENTRY1(NOP, nop,v), /* reserved NOP */ [0x1d] =3D X86_OP_ENTRY1(NOP, nop,v), /* reserved NOP */ [0x1e] =3D X86_OP_ENTRY1(NOP, nop,v), /* reserved NOP */ @@ -1780,6 +1785,19 @@ static const X86OpEntry opcodes_root[256] =3D { [0xCE] =3D X86_OP_ENTRY0(INTO), [0xCF] =3D X86_OP_ENTRY0(IRET, chk(vm86_iopl) svm(IRET)), =20 + /* + * x87 is nolea because it needs the address without segment base, + * in order to store it in fdp. + */ + [0xD8] =3D X86_OP_ENTRY1(x87, nop,v, nolea), + [0xD9] =3D X86_OP_ENTRY1(x87, nop,v, nolea), + [0xDA] =3D X86_OP_ENTRY1(x87, nop,v, nolea), + [0xDB] =3D X86_OP_ENTRY1(x87, nop,v, nolea), + [0xDC] =3D X86_OP_ENTRY1(x87, nop,v, nolea), + [0xDD] =3D X86_OP_ENTRY1(x87, nop,v, nolea), + [0xDE] =3D X86_OP_ENTRY1(x87, nop,v, nolea), + [0xDF] =3D X86_OP_ENTRY1(x87, nop,v, nolea), + [0xE8] =3D X86_OP_ENTRYr(CALL, J,z_f64), [0xE9] =3D X86_OP_ENTRYr(JMP, J,z_f64), [0xEA] =3D X86_OP_ENTRYrr(JMPF, I_unsigned,p, I_unsigned,w, chk(i64)), @@ -2608,30 +2626,6 @@ static void disas_insn(DisasContext *s, CPUState *cp= u) } } =20 - /* Go back to old decoder for unconverted opcodes. */ - if (!(s->prefix & PREFIX_VEX)) { - if ((b & ~7) =3D=3D 0xd8) { - if (!disas_insn_x87(s, cpu, b)) { - goto unknown_op; - } - return; - } - - if (b =3D=3D 0x0f) { - b =3D x86_ldub_code(env, s); - switch (b) { - case 0x00 ... 0x01: /* mostly privileged instructions */ - case 0x1a ... 0x1b: /* MPX */ - case 0xc7: /* grp9 */ - disas_insn_old(s, cpu, b + 0x100); - return; - default: - decode_func =3D do_decode_0F; - break; - } - } - } - memset(&decode, 0, sizeof(decode)); decode.cc_op =3D -1; decode.b =3D b; @@ -2728,6 +2722,15 @@ static void disas_insn(DisasContext *s, CPUState *cp= u) break; } =20 + /* + * hack for old decoder: 0F C7 has both instructions that accept LOCK + * and instructions that don't, but also needs X86_SPECIAL_NoLoadEA. + * Keep this here until CMPXCHG8B/CMPXCHG16B is separated from the + * other unconverted opcodes. + */ + if (decode.e.gen =3D=3D gen_multi0F) { + accept_lock =3D true; + } if ((s->prefix & PREFIX_LOCK) && !accept_lock) { goto illegal_op; } @@ -2775,7 +2778,7 @@ static void disas_insn(DisasContext *s, CPUState *cpu) =20 if (decode.e.special !=3D X86_SPECIAL_NoLoadEA && (decode.op[0].has_ea || decode.op[1].has_ea || decode.op[2].has_ea= )) { - gen_load_ea(s, &decode); + gen_lea_modrm(s, &decode); } if (s->prefix & PREFIX_LOCK) { gen_load(s, &decode, 2, s->T1); diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc index a25dff0570c..edadb51ae89 100644 --- a/target/i386/tcg/emit.c.inc +++ b/target/i386/tcg/emit.c.inc @@ -73,7 +73,7 @@ static void gen_NM_exception(DisasContext *s) gen_exception(s, EXCP07_PREX); } =20 -static void gen_load_ea(DisasContext *s, X86DecodedInsn *decode) +static void gen_lea_modrm(DisasContext *s, X86DecodedInsn *decode) { AddressParts *mem =3D &decode->mem; TCGv ea; --=20 2.45.2