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([2804:7f0:b401:1758:3e7c:3fff:fe7a:e83b]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-716b4a73183sm3953601a12.39.2024.06.23.22.31.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Jun 2024 22:31:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1719207086; x=1719811886; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yW6AGmqZg/Umn21wD61FD4HlSpwe58RxaApVtS3jS0Y=; b=BzDPyHsygGp4JzmQB9B87UMD3x+7/OEisMPQhm4MeBfqdEJA+18Co+JqPexSwZm0ge WttEB63JVCmV+wFPEy+ztM/jzzNCQ+gsU2XX0P7c8bMEUrnN4PJ9hS43bNak9ihXlCit TU1BK2fkQiKKWDwMgQDXLJS/Fo0YWHTi7xM5fs+dmiYtD5OnD+ju9N9arDEdXvid8XVG J6bPaJOKtQ0Oa52kdF3gG9DAvUU/NXiHXZ3X7YuE48e435LfDaalDRhtubo2KPCtm4Et n7UOBtM3CS8lwygOLaFwMyH0/duAybnHikYUCXZJ4Th/W0E6LxBsxpK7m4Z+DjzgAa0r W0Hw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1719207086; x=1719811886; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yW6AGmqZg/Umn21wD61FD4HlSpwe58RxaApVtS3jS0Y=; b=DwWoKMs1ohv8239o47cz66W0ytjTLnWLmjRSnjV5Z+kDbRTNW0vnWqo5p8s+lnlZU0 BGUQHwKO7lcwpHemCCy/Kq1Gc89tLJtIjt36E5KY5qEFnReFWUc0w/+eRCp8CibXNSjd WUlMQrI5nUEtx5I/mUkGd1hW/OfDfKdgtEYob+YUW/TzxQ2b4O2FLx7SUnZjezKCWjXn XRoI5rhQGKKAjIoELLx+oCECM/wtFRcXx3i+wKzTDxRybd8PmZj7w1Lw0CZKQRf3Eemn 6/K+iiFyTTE1glRZ2JUpjrXXhueCR3zLqQgZF2J5vfz3K6X9qO582vNKo6fzibW/W8YH kBtg== X-Gm-Message-State: AOJu0YytE+teJ1ctgAMpuLSAi8/Zot+ykZl5fo2ZL0DaWnN+D7NPR5XE bb2y7nnyoIhlXxS+98qtwbuf7DlFuSSfRDqJtZ6n4/luZ6jdEpkwSTtMelhU2zaE6+KxgS5/ljT LpBI= X-Google-Smtp-Source: AGHT+IGaKFzw8ochNjV4BIJrIVZRS8hdT3fA0tQ1OmwU93h44sejt3+S0AyAGqTpqzQS2eEUvrg02w== X-Received: by 2002:a05:6358:5e15:b0:19f:4ca6:86bf with SMTP id e5c5f4694b2df-1a23c1ccdfdmr483884055d.32.1719207085733; Sun, 23 Jun 2024 22:31:25 -0700 (PDT) From: Gustavo Romero To: qemu-devel@nongnu.org, alex.bennee@linaro.org, richard.henderson@linaro.org Cc: philmd@linaro.org, peter.maydell@linaro.org, gustavo.romero@linaro.org Subject: [PATCH v4 6/9] target/arm: Factor out code for setting MTE TCF0 field Date: Mon, 24 Jun 2024 05:30:43 +0000 Message-Id: <20240624053046.221802-7-gustavo.romero@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240624053046.221802-1-gustavo.romero@linaro.org> References: <20240624053046.221802-1-gustavo.romero@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c2f; envelope-from=gustavo.romero@linaro.org; helo=mail-oo1-xc2f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1719207159509100003 Content-Type: text/plain; charset="utf-8" Factor out the code used for setting the MTE TCF0 field from the prctl code into a convenient function. Other subsystems, like gdbstub, need to set this field as well, so keep it as a separate function to avoid duplication and ensure consistency in how this field is set across the board. Signed-off-by: Gustavo Romero --- linux-user/aarch64/mte_user_helper.h | 38 ++++++++++++++++++++++++++++ linux-user/aarch64/target_prctl.h | 22 ++-------------- 2 files changed, 40 insertions(+), 20 deletions(-) create mode 100644 linux-user/aarch64/mte_user_helper.h diff --git a/linux-user/aarch64/mte_user_helper.h b/linux-user/aarch64/mte_= user_helper.h new file mode 100644 index 0000000000..fd92e71c00 --- /dev/null +++ b/linux-user/aarch64/mte_user_helper.h @@ -0,0 +1,38 @@ +/* + * ARM MemTag convenience functions. + * + * This code is licensed under the GNU GPL v2 or later. + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#ifndef MTE_H +#define MTE_H + +#include "sys/prctl.h" + +static inline void arm_set_mte_tcf0(CPUArchState *env, abi_long value) +{ + /* + * Write PR_MTE_TCF to SCTLR_EL1[TCF0]. + * + * The kernel has a per-cpu configuration for the sysadmin, + * /sys/devices/system/cpu/cpu/mte_tcf_preferred, + * which qemu does not implement. + * + * Because there is no performance difference between the modes, and + * because SYNC is most useful for debugging MTE errors, choose SYNC + * as the preferred mode. With this preference, and the way the API + * uses only two bits, there is no way for the program to select + * ASYMM mode. + */ + unsigned tcf =3D 0; + if (value & PR_MTE_TCF_SYNC) { + tcf =3D 1; + } else if (value & PR_MTE_TCF_ASYNC) { + tcf =3D 2; + } + env->cp15.sctlr_el[1] =3D deposit64(env->cp15.sctlr_el[1], 38, 2, tcf); +} + +#endif /* MTE_H */ diff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_= prctl.h index aa8e203c15..ed75b9e4b5 100644 --- a/linux-user/aarch64/target_prctl.h +++ b/linux-user/aarch64/target_prctl.h @@ -7,6 +7,7 @@ #define AARCH64_TARGET_PRCTL_H =20 #include "target/arm/cpu-features.h" +#include "mte_user_helper.h" =20 static abi_long do_prctl_sve_get_vl(CPUArchState *env) { @@ -173,26 +174,7 @@ static abi_long do_prctl_set_tagged_addr_ctrl(CPUArchS= tate *env, abi_long arg2) env->tagged_addr_enable =3D arg2 & PR_TAGGED_ADDR_ENABLE; =20 if (cpu_isar_feature(aa64_mte, cpu)) { - /* - * Write PR_MTE_TCF to SCTLR_EL1[TCF0]. - * - * The kernel has a per-cpu configuration for the sysadmin, - * /sys/devices/system/cpu/cpu/mte_tcf_preferred, - * which qemu does not implement. - * - * Because there is no performance difference between the modes, a= nd - * because SYNC is most useful for debugging MTE errors, choose SY= NC - * as the preferred mode. With this preference, and the way the A= PI - * uses only two bits, there is no way for the program to select - * ASYMM mode. - */ - unsigned tcf =3D 0; - if (arg2 & PR_MTE_TCF_SYNC) { - tcf =3D 1; - } else if (arg2 & PR_MTE_TCF_ASYNC) { - tcf =3D 2; - } - env->cp15.sctlr_el[1] =3D deposit64(env->cp15.sctlr_el[1], 38, 2, = tcf); + arm_set_mte_tcf0(env, arg2); =20 /* * Write PR_MTE_TAG to GCR_EL1[Exclude]. --=20 2.34.1