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Mon, 24 Jun 2024 13:19:45 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, tjeznach@rivosinc.com, frank.chang@sifive.com, jason.chien@sifive.com, Daniel Henrique Barboza Subject: [PATCH v4 14/14] docs/specs: add riscv-iommu Date: Mon, 24 Jun 2024 17:18:24 -0300 Message-ID: <20240624201825.1054980-15-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240624201825.1054980-1-dbarboza@ventanamicro.com> References: <20240624201825.1054980-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1719260395731100001 Content-Type: text/plain; charset="utf-8" Add a simple guideline to use the existing RISC-V IOMMU support we just added. This doc will be updated once we add the riscv-iommu-sys device. Signed-off-by: Daniel Henrique Barboza --- docs/specs/index.rst | 1 + docs/specs/riscv-iommu.rst | 55 ++++++++++++++++++++++++++++++++++++++ docs/system/riscv/virt.rst | 13 +++++++++ 3 files changed, 69 insertions(+) create mode 100644 docs/specs/riscv-iommu.rst diff --git a/docs/specs/index.rst b/docs/specs/index.rst index 1484e3e760..c68cd9ae6c 100644 --- a/docs/specs/index.rst +++ b/docs/specs/index.rst @@ -33,3 +33,4 @@ guest hardware that is specific to QEMU. virt-ctlr vmcoreinfo vmgenid + riscv-iommu diff --git a/docs/specs/riscv-iommu.rst b/docs/specs/riscv-iommu.rst new file mode 100644 index 0000000000..fa38ff7667 --- /dev/null +++ b/docs/specs/riscv-iommu.rst @@ -0,0 +1,55 @@ +.. _riscv-iommu: + +RISC-V IOMMU support for RISC-V machines +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +QEMU implements a RISC-V IOMMU emulation based on the RISC-V IOMMU spec +version 1.0 [1]. + +The emulation includes a PCI reference device, riscv-iommu-pci, that QEMU +RISC-V boards can use. The 'virt' RISC-V machine is compatible with this +device. + +A platform device that implements the RISC-V IOMMU will be added in the +future. + + +riscv-iommu-pci reference device +-------------------------------- + +This device implements the RISC-V IOMMU emulation as recommended by the se= ction +"Integrating an IOMMU as a PCIe device" of [1]: a PCI device with base cla= ss 08h, +sub-class 06h and programming interface 00h. + +As a reference device it doesn't implement anything outside of the specifi= cation, +so it uses a generic default PCI ID given by QEMU: 1b36:0014. + +To include the device in the 'virt' machine: + +.. code-block:: bash + + $ qemu-system-riscv64 -M virt -device riscv-iommu-pci (...) + +As of this writing the existing Linux kernel support [2], not yet merged, = is being +created as a Rivos device, i.e. it uses Rivos vendor ID. To use the riscv= -iommu-pci +device with the existing kernel support we need to emulate a Rivos PCI IOM= MU by +setting 'vendor-id' and 'device-id': + +.. code-block:: bash + + $ qemu-system-riscv64 -M virt \ + -device riscv-iommu-pci,vendor-id=3D0x1efd,device-id=3D0xedf1 (...) + +Several options are available to control the capabilities of the device, n= amely: + +- "bus" +- "ioatc-limit" +- "intremap" +- "ats" +- "off" (Out-of-reset translation mode: 'on' for DMA disabled, 'off' for '= BARE' (passthrough)) +- "s-stage" +- "g-stage" + + +[1] https://github.com/riscv-non-isa/riscv-iommu/releases/download/v1.0/ri= scv-iommu.pdf +[2] https://lore.kernel.org/linux-riscv/cover.1718388908.git.tjeznach@rivo= sinc.com/ diff --git a/docs/system/riscv/virt.rst b/docs/system/riscv/virt.rst index 9a06f95a34..8e9a2e4dda 100644 --- a/docs/system/riscv/virt.rst +++ b/docs/system/riscv/virt.rst @@ -84,6 +84,19 @@ none``, as in =20 Firmware images used for pflash must be exactly 32 MiB in size. =20 +riscv-iommu support +------------------- + +The board has support for the riscv-iommu-pci device by using the following +command line: + +.. code-block:: bash + + $ qemu-system-riscv64 -M virt -device riscv-iommu-pci (...) + +Refer to :ref:`riscv-iommu` for more information on how the RISC-V IOMMU s= upport +works. + Machine-specific options ------------------------ =20 --=20 2.45.2