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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1719298740; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=B20vDn+y9X1k1NJBIFC+mmYFczc3oyCRES/8ggOE9QQ=; b=g/iUwGsbsNngkdje/YkpmuJ4rEbpUXVx57JVS3PJzdgr7zZkPMH1y5UzQYEx8pYsFAcnZD h2yCf7BZy0dMCiVjYO96ctxuDqvxEGuijW/wb+7zSn2yOCmM+JdPGFWFN88Ba72hlm6eP7 MVniQMdpboK4h/64OydS1aD/mNiIvJk= X-MC-Unique: OLL8hd-fPFWytE2fRww-qA-1 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Peter Maydell , Joel Stanley , Andrew Jeffery , Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH] aspeed/sdmc: Check RAM size value at realize time Date: Tue, 25 Jun 2024 08:58:39 +0200 Message-ID: <20240625065839.485034-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: 10 X-Spam_score: 1.0 X-Spam_bar: + X-Spam_report: (1.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.207, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1719298772673100003 The RAM size of the SDMC device is validated for the SoC and set when the Aspeed machines are initialized and then later used by several SoC implementations. However, the SDMC model never checks that the RAM size has been actually set before being used. Do that at realize. Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: Jamin_lin < jamin_lin@aspeedtech.com> --- hw/misc/aspeed_sdmc.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c index 94eed9264d09..ebf139cb5c91 100644 --- a/hw/misc/aspeed_sdmc.c +++ b/hw/misc/aspeed_sdmc.c @@ -271,6 +271,12 @@ static void aspeed_sdmc_realize(DeviceState *dev, Erro= r **errp) AspeedSDMCClass *asc =3D ASPEED_SDMC_GET_CLASS(s); =20 assert(asc->max_ram_size < 4 * GiB || asc->is_bus64bit); + + if (!s->ram_size) { + error_setg(errp, "RAM size is not set"); + return; + } + s->max_ram_size =3D asc->max_ram_size; =20 memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_sdmc_ops, s, --=20 2.45.2