From: Frank Chang <frank.chang@sifive.com>

Currently, the implied extensions are enabled and checked in
riscv_cpu_validate_set_extensions(). However, the order of enabling the
implied extensions must follow a strict sequence, which is error-prone.

This patchset introduce extension implied rule helpers to enable the
implied extensions. This also eliminates the old-fashioned ordering
requirement. For example, Zvksg implies Zvks, Zvks implies Zvksed, etc.,
removing the need to check the implied rules of Zvksg before Zvks.

The idea [1] and the implied rules [2] are referenced from LLVM.

[1] https://github.com/llvm/llvm-project/blob/main/llvm/lib/TargetParser/RISCVISAInfo.cpp#L875
[2] https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/RISCV/RISCVFeatures.td

Changelog:

v3:
  - Replace the enabled bitmask of type 'uint64_t' with a dynamic bitmask
    to support more than 64 harts.
  - Ensure that implied rules and hash tables are initialized/created only once.
  - Rename variables to align nomenclature with existing variables:
      - In RISCVCPUImpliedExtsRule structure:
        - 'implied_misas' -> 'implied_misa_exts'
        - 'implied_exts' -> 'implied_multi_exts'
      - 'misa_implied_rules' -> 'misa_ext_implied_rules'
      - 'ext_implied_rules' -> 'multi_ext_implied_rules'
      - 'riscv_misa_implied_rules' -> 'riscv_misa_ext_implied_rules'
      - 'riscv_ext_implied_rules -> 'riscv_multi_ext_implied_rules'

v2:
  - Remove enabled bitmask from user-mode QEMU as there's no good way
    (e.g. mhartid) to distinguish the SMP cores in user-mode QEMU.
  - Use qatomic API to access the enabled bitmask to prevent the
    potential enabled bit from being cleared by another hart.

Frank Chang (6):
  target/riscv: Introduce extension implied rules definition
  target/riscv: Introduce extension implied rule helpers
  target/riscv: Add MISA extension implied rules
  target/riscv: Add multi extension implied rules
  target/riscv: Add Zc extension implied rule
  target/riscv: Remove extension auto-update check statements

 target/riscv/cpu.c         | 396 +++++++++++++++++++++++++++++++++++++
 target/riscv/cpu.h         |  23 +++
 target/riscv/tcg/tcg-cpu.c | 274 ++++++++++++++-----------
 3 files changed, 574 insertions(+), 119 deletions(-)

--
2.43.2

On Tue, Jun 25, 2024 at 9:48 PM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> Currently, the implied extensions are enabled and checked in
> riscv_cpu_validate_set_extensions(). However, the order of enabling the
> implied extensions must follow a strict sequence, which is error-prone.
>
> This patchset introduce extension implied rule helpers to enable the
> implied extensions. This also eliminates the old-fashioned ordering
> requirement. For example, Zvksg implies Zvks, Zvks implies Zvksed, etc.,
> removing the need to check the implied rules of Zvksg before Zvks.
>
> The idea [1] and the implied rules [2] are referenced from LLVM.
>
> [1] https://github.com/llvm/llvm-project/blob/main/llvm/lib/TargetParser/RISCVISAInfo.cpp#L875
> [2] https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/RISCV/RISCVFeatures.td
>
> Changelog:
>
> v3:
>   - Replace the enabled bitmask of type 'uint64_t' with a dynamic bitmask
>     to support more than 64 harts.
>   - Ensure that implied rules and hash tables are initialized/created only once.
>   - Rename variables to align nomenclature with existing variables:
>       - In RISCVCPUImpliedExtsRule structure:
>         - 'implied_misas' -> 'implied_misa_exts'
>         - 'implied_exts' -> 'implied_multi_exts'
>       - 'misa_implied_rules' -> 'misa_ext_implied_rules'
>       - 'ext_implied_rules' -> 'multi_ext_implied_rules'
>       - 'riscv_misa_implied_rules' -> 'riscv_misa_ext_implied_rules'
>       - 'riscv_ext_implied_rules -> 'riscv_multi_ext_implied_rules'
>
> v2:
>   - Remove enabled bitmask from user-mode QEMU as there's no good way
>     (e.g. mhartid) to distinguish the SMP cores in user-mode QEMU.
>   - Use qatomic API to access the enabled bitmask to prevent the
>     potential enabled bit from being cleared by another hart.
>
> Frank Chang (6):
>   target/riscv: Introduce extension implied rules definition
>   target/riscv: Introduce extension implied rule helpers
>   target/riscv: Add MISA extension implied rules
>   target/riscv: Add multi extension implied rules
>   target/riscv: Add Zc extension implied rule
>   target/riscv: Remove extension auto-update check statements

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  target/riscv/cpu.c         | 396 +++++++++++++++++++++++++++++++++++++
>  target/riscv/cpu.h         |  23 +++
>  target/riscv/tcg/tcg-cpu.c | 274 ++++++++++++++-----------
>  3 files changed, 574 insertions(+), 119 deletions(-)
>
> --
> 2.43.2
>
>