In AArch32, the floating point control and status bits are all in a
single register, FPSCR.  In AArch64, these were split into separate
FPCR and FPSR registers, but the bit layouts remained the same, with
no overlaps, so that you could construct an FPSCR value by ORing FPCR
and FPSR, or equivalently could produce FPSR and FPCR by masking an
FPSCR value.  For QEMU's implementation, we opted to use masking to
produce FPSR and FPCR, because we started with an AArch32
implementation of FPSCR.

The addition of the (AArch64-only) FEAT_AFP adds new bits to the FPCR
which overlap with some bits in the FPSR.  This means we'll no longer
be able to consider the FPSCR-encoded value as the primary one, but
instead need to treat FPSR/FPCR as the primary encoding and construct
the FPSCR from those.  (This remains possible because the FEAT_AFP
bits in FPCR don't appear in the FPSCR.)

This patchseries does the necessary refactoring to our handling
of FPCR and FPSR to allow us to implement the new FPCR-only bits:
 * we flip vfp_{get,set}_fpscr() and vfp_{get,set}_{fpcr,fpsr}()
   so that the former call the latter rather than the other way round
 * we make the migration code send FPSR and FPCR separately when there's
   a bit set which can't be represented in the FPSCR format
   (we continue to use the FPSCR format on the wire when possible,
   for migration backwards-compatibility)
 * we store the FPCR and FPSR in the CPU state struct in new
   vfp.fpcr and vfp.fpsr fields, rather than in vfp.xregs[ARM_VFP_FPSCR]
 * we make sure that writes to FPSCR leave bits in FPCR that aren't
   in FPSCR alone

The series also has a bit of tidyup of some of the macro naming etc.

thanks
-- PMM

Peter Maydell (9):
  target/arm: Correct comments about M-profile FPSCR
  target/arm: Make vfp_get_fpscr() call vfp_get_{fpcr,fpsr}
  target/arm: Make vfp_set_fpscr() call vfp_set_{fpcr,fpsr}
  target/arm: Support migration when FPSR/FPCR won't fit in the FPSCR
  target/arm: Implement store_cpu_field_low32() macro
  target/arm: Store FPSR and FPCR in separate CPU state fields
  target/arm: Rename FPCR_ QC, NZCV macros to FPSR_
  target/arm: Rename FPSR_MASK and FPCR_MASK and define them
    symbolically
  target/arm: Allow FPCR bits that aren't in FPSCR

 target/arm/cpu.h                  | 109 ++++++++++++-----
 target/arm/tcg/translate-a32.h    |   7 ++
 target/arm/tcg/translate.h        |   3 +-
 target/arm/machine.c              | 135 ++++++++++++++++++++-
 target/arm/tcg/mve_helper.c       |  12 +-
 target/arm/tcg/translate-m-nocp.c |  22 ++--
 target/arm/tcg/translate-vfp.c    |   4 +-
 target/arm/vfp_helper.c           | 187 +++++++++++++++++++-----------
 8 files changed, 356 insertions(+), 123 deletions(-)

-- 
2.34.1