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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4256af55c0asm37180945e9.15.2024.06.28.07.23.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Jun 2024 07:23:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1719584636; x=1720189436; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=uem/v2axAJA0BB1dpydfxHH8U9BEMfWx4sO4XmB5FGg=; b=LO6DA8gpEHR9mn5CMU7NNz+nWMpB2Zh5YbCed+h1r61DWFIUF76hYgiDLkcOyEqNhD b31vsFc++JgAnPh96r3vT7jq36A0SNj3Vkiz/ONt5GvDYPWn+YUAS1XoAghq0KE9aMP7 rNQS3EPo+IbIxPkkRTCaKPW5THNx6/NEvF2zKNzbopJswo2MpN6ASK5MvLlsR4MbhIKI YevdqNztCPIC4iheyjiX2HAtn3tLk2kI/DpRmhrXOCaFqVQH83GDC5qug1BaDUP2miyx xc/XJM+7ifcsCKr1OjpnVlI/2JZ68yY4NI2HV+qEZsfzR9WXct7GE31KMeBZg32fQauO RlAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1719584636; x=1720189436; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uem/v2axAJA0BB1dpydfxHH8U9BEMfWx4sO4XmB5FGg=; b=rO4iwKK6nspZHBwYkHuryoABT08wswBiGoqz1tLeEPu0Pd0C7IxdctbaEQZ8PhAl4D lhOPsLrlK5/mnvv38++8SPZv4NC5cPS2uBqzFefYlwMHl5Dbmu2ZrdLiLKnaRWoXES1L /AAfH22hKT9P2ZxhFLBFU4UoiVRhlCCnIzDZa4wOc3hOXuA9ob6Ow1ZTUQSqFqXtL427 JrIA1yE1R3/9BDW3pu4f8YC22Eg7XX5A7Z2sywgvldfxsuPgA6MYUlTzxaZCVpEuiiNX fhN408lPt6Ab+yYbx7a3GnFN+htveVJRp7vqkgryj25ilqooQtG1cwPlXsxoOnKrk/37 co0w== X-Forwarded-Encrypted: i=1; AJvYcCXSYOFdgGxrHjknhfncFTd0O3TPcm4PxL2IwLlB5yfzVdEyneOKbmevbndNNfjoPgzF14NYq1YSgKi1ZmU5UtqG75Jp17Y= X-Gm-Message-State: AOJu0YwzqWMuTPNXAJ4Yp0xDt4SBCxOBN3vvIrK9zI32e7JfCCG/aNWi sW75sPEeB0Y1+B+RU/BhPJ/cyHD6PvOcL0JpjT3yDtI27WIVr0lvwqILu0wQYts= X-Google-Smtp-Source: AGHT+IH5fDky1iDheHciv83SBIKGthfDA03HpqmV873ctQPmr7grLSbe7cnYnHLoNqYxlo9qgFmDCA== X-Received: by 2002:a2e:8048:0:b0:2ee:4f58:7738 with SMTP id 38308e7fff4ca-2ee4f5878f3mr24804511fa.17.1719584636538; Fri, 28 Jun 2024 07:23:56 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 7/9] target/arm: Rename FPCR_ QC, NZCV macros to FPSR_ Date: Fri, 28 Jun 2024 15:23:45 +0100 Message-Id: <20240628142347.1283015-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240628142347.1283015-1-peter.maydell@linaro.org> References: <20240628142347.1283015-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::236; envelope-from=peter.maydell@linaro.org; helo=mail-lj1-x236.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1719584706954100008 Content-Type: text/plain; charset="utf-8" The QC, N, Z, C, V bits live in the FPSR, not the FPCR. Rename the macros that define these bits accordingly. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 17 ++++++++++------- target/arm/tcg/mve_helper.c | 8 ++++---- target/arm/tcg/translate-m-nocp.c | 16 ++++++++-------- target/arm/tcg/translate-vfp.c | 2 +- target/arm/vfp_helper.c | 8 ++++---- 5 files changed, 27 insertions(+), 24 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 2eb7fc3bc39..9d226c474d2 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1697,6 +1697,7 @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val); #define FPSR_MASK 0xf800009f #define FPCR_MASK 0x07ff9f00 =20 +/* FPCR bits */ #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable= */ #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */ #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ @@ -1708,18 +1709,20 @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val); #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ #define FPCR_DN (1 << 25) /* Default NaN enable bit */ #define FPCR_AHP (1 << 26) /* Alternative half-precision */ -#define FPCR_QC (1 << 27) /* Cumulative saturation bit */ -#define FPCR_V (1 << 28) /* FP overflow flag */ -#define FPCR_C (1 << 29) /* FP carry flag */ -#define FPCR_Z (1 << 30) /* FP zero flag */ -#define FPCR_N (1 << 31) /* FP negative flag */ =20 #define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */ #define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT) #define FPCR_LTPSIZE_LENGTH 3 =20 -#define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V) -#define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC) +/* FPSR bits */ +#define FPSR_QC (1 << 27) /* Cumulative saturation bit */ +#define FPSR_V (1 << 28) /* FP overflow flag */ +#define FPSR_C (1 << 29) /* FP carry flag */ +#define FPSR_Z (1 << 30) /* FP zero flag */ +#define FPSR_N (1 << 31) /* FP negative flag */ + +#define FPSR_NZCV_MASK (FPSR_N | FPSR_Z | FPSR_C | FPSR_V) +#define FPSR_NZCVQC_MASK (FPSR_NZCV_MASK | FPSR_QC) =20 /** * vfp_get_fpsr: read the AArch64 FPSR diff --git a/target/arm/tcg/mve_helper.c b/target/arm/tcg/mve_helper.c index 234f395b093..03ebef5ef21 100644 --- a/target/arm/tcg/mve_helper.c +++ b/target/arm/tcg/mve_helper.c @@ -1115,21 +1115,21 @@ static void do_vadc(CPUARMState *env, uint32_t *d, = uint32_t *n, uint32_t *m, =20 if (update_flags) { /* Store C, clear NZV. */ - env->vfp.fpsr &=3D ~FPCR_NZCV_MASK; - env->vfp.fpsr |=3D carry_in * FPCR_C; + env->vfp.fpsr &=3D ~FPSR_NZCV_MASK; + env->vfp.fpsr |=3D carry_in * FPSR_C; } mve_advance_vpt(env); } =20 void HELPER(mve_vadc)(CPUARMState *env, void *vd, void *vn, void *vm) { - bool carry_in =3D env->vfp.fpsr & FPCR_C; + bool carry_in =3D env->vfp.fpsr & FPSR_C; do_vadc(env, vd, vn, vm, 0, carry_in, false); } =20 void HELPER(mve_vsbc)(CPUARMState *env, void *vd, void *vn, void *vm) { - bool carry_in =3D env->vfp.fpsr & FPCR_C; + bool carry_in =3D env->vfp.fpsr & FPSR_C; do_vadc(env, vd, vn, vm, -1, carry_in, false); } =20 diff --git a/target/arm/tcg/translate-m-nocp.c b/target/arm/tcg/translate-m= -nocp.c index 875f6a8725d..b92773b4af5 100644 --- a/target/arm/tcg/translate-m-nocp.c +++ b/target/arm/tcg/translate-m-nocp.c @@ -332,7 +332,7 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int = regno, if (dc_isar_feature(aa32_mve, s)) { /* QC is only present for MVE; otherwise RES0 */ TCGv_i32 qc =3D tcg_temp_new_i32(); - tcg_gen_andi_i32(qc, tmp, FPCR_QC); + tcg_gen_andi_i32(qc, tmp, FPSR_QC); /* * The 4 vfp.qc[] fields need only be "zero" vs "non-zero"; * here writing the same value into all elements is simplest. @@ -340,9 +340,9 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int = regno, tcg_gen_gvec_dup_i32(MO_32, offsetof(CPUARMState, vfp.qc), 16, 16, qc); } - tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK); + tcg_gen_andi_i32(tmp, tmp, FPSR_NZCV_MASK); fpscr =3D load_cpu_field_low32(vfp.fpsr); - tcg_gen_andi_i32(fpscr, fpscr, ~FPCR_NZCV_MASK); + tcg_gen_andi_i32(fpscr, fpscr, ~FPSR_NZCV_MASK); tcg_gen_or_i32(fpscr, fpscr, tmp); store_cpu_field_low32(fpscr, vfp.fpsr); break; @@ -390,7 +390,7 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int = regno, tcg_gen_deposit_i32(control, control, sfpa, R_V7M_CONTROL_SFPA_SHIFT, 1); store_cpu_field(control, v7m.control[M_REG_S]); - tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK); + tcg_gen_andi_i32(tmp, tmp, ~FPSR_NZCV_MASK); gen_helper_vfp_set_fpscr(tcg_env, tmp); s->base.is_jmp =3D DISAS_UPDATE_NOCHAIN; break; @@ -457,7 +457,7 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int r= egno, case ARM_VFP_FPSCR_NZCVQC: tmp =3D tcg_temp_new_i32(); gen_helper_vfp_get_fpscr(tmp, tcg_env); - tcg_gen_andi_i32(tmp, tmp, FPCR_NZCVQC_MASK); + tcg_gen_andi_i32(tmp, tmp, FPSR_NZCVQC_MASK); storefn(s, opaque, tmp, true); break; case QEMU_VFP_FPSCR_NZCV: @@ -466,7 +466,7 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int r= egno, * helper call for the "VMRS to CPSR.NZCV" insn. */ tmp =3D load_cpu_field_low32(vfp.fpsr); - tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK); + tcg_gen_andi_i32(tmp, tmp, FPSR_NZCV_MASK); storefn(s, opaque, tmp, true); break; case ARM_VFP_FPCXT_S: @@ -476,7 +476,7 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int r= egno, tmp =3D tcg_temp_new_i32(); sfpa =3D tcg_temp_new_i32(); gen_helper_vfp_get_fpscr(tmp, tcg_env); - tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK); + tcg_gen_andi_i32(tmp, tmp, ~FPSR_NZCV_MASK); control =3D load_cpu_field(v7m.control[M_REG_S]); tcg_gen_andi_i32(sfpa, control, R_V7M_CONTROL_SFPA_MASK); tcg_gen_shli_i32(sfpa, sfpa, 31 - R_V7M_CONTROL_SFPA_SHIFT); @@ -529,7 +529,7 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int r= egno, sfpa =3D tcg_temp_new_i32(); fpscr =3D tcg_temp_new_i32(); gen_helper_vfp_get_fpscr(fpscr, tcg_env); - tcg_gen_andi_i32(tmp, fpscr, ~FPCR_NZCV_MASK); + tcg_gen_andi_i32(tmp, fpscr, ~FPSR_NZCV_MASK); control =3D load_cpu_field(v7m.control[M_REG_S]); tcg_gen_andi_i32(sfpa, control, R_V7M_CONTROL_SFPA_MASK); tcg_gen_shli_i32(sfpa, sfpa, 31 - R_V7M_CONTROL_SFPA_SHIFT); diff --git a/target/arm/tcg/translate-vfp.c b/target/arm/tcg/translate-vfp.c index 0d9788e8103..cd5b8483576 100644 --- a/target/arm/tcg/translate-vfp.c +++ b/target/arm/tcg/translate-vfp.c @@ -834,7 +834,7 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_V= MRS *a) case ARM_VFP_FPSCR: if (a->rt =3D=3D 15) { tmp =3D load_cpu_field_low32(vfp.fpsr); - tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK); + tcg_gen_andi_i32(tmp, tmp, FPSR_NZCV_MASK); } else { tmp =3D tcg_temp_new_i32(); gen_helper_vfp_get_fpscr(tmp, tcg_env); diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index f7a3da7f68b..1ac0142e10f 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -196,7 +196,7 @@ uint32_t vfp_get_fpsr(CPUARMState *env) fpsr |=3D vfp_get_fpsr_from_host(env); =20 i =3D env->vfp.qc[0] | env->vfp.qc[1] | env->vfp.qc[2] | env->vfp.qc[3= ]; - fpsr |=3D i ? FPCR_QC : 0; + fpsr |=3D i ? FPSR_QC : 0; return fpsr; } =20 @@ -222,7 +222,7 @@ void vfp_set_fpsr(CPUARMState *env, uint32_t val) * The bit we set within fpscr_q is arbitrary; the register as a * whole being zero/non-zero is what counts. */ - env->vfp.qc[0] =3D val & FPCR_QC; + env->vfp.qc[0] =3D val & FPSR_QC; env->vfp.qc[1] =3D 0; env->vfp.qc[2] =3D 0; env->vfp.qc[3] =3D 0; @@ -234,7 +234,7 @@ void vfp_set_fpsr(CPUARMState *env, uint32_t val) * fp_status, and QC is in vfp.qc[]. Store the NZCV bits there, * and zero any of the other FPSR bits. */ - val &=3D FPCR_NZCV_MASK; + val &=3D FPSR_NZCV_MASK; env->vfp.fpsr =3D val; } =20 @@ -1156,7 +1156,7 @@ uint32_t HELPER(vjcvt)(float64 value, CPUARMState *en= v) uint32_t z =3D (pair >> 32) =3D=3D 0; =20 /* Store Z, clear NCV, in FPSCR.NZCV. */ - env->vfp.fpsr =3D (env->vfp.fpsr & ~FPCR_NZCV_MASK) | (z * FPCR_Z); + env->vfp.fpsr =3D (env->vfp.fpsr & ~FPSR_NZCV_MASK) | (z * FPSR_Z); =20 return result; } --=20 2.34.1