From nobody Sat Dec 28 09:56:35 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=ilande.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1719590666925446.55554358539916; Fri, 28 Jun 2024 09:04:26 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sNE4j-0000A7-Qa; Fri, 28 Jun 2024 12:03:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sNE4h-00009X-Vg; Fri, 28 Jun 2024 12:03:48 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sNE4g-0003cq-ED; Fri, 28 Jun 2024 12:03:47 -0400 Received: from [2a00:23c4:8bb4:4000:71e:fc91:de8e:dcdf] (helo=localhost.localdomain) by mail.ilande.co.uk with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1sNE3D-000Ckz-VZ; Fri, 28 Jun 2024 17:02:20 +0100 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=ilande.co.uk; s=20220518; h=Subject:Content-Transfer-Encoding:MIME-Version: Message-Id:Date:To:From:Sender:Reply-To:Cc:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:In-Reply-To:References; bh=WaAoBcgo7k61xF3uC78O3ZkwuohN+ViE1F4wyqm1BOY=; b=uwEo0y9CXJsvqfGX5WgEAVx+ZZ QiLFKNTLsvg4PXlRYW0cB268jTHlkS75kH1E8aOx1w6bYaFmKgviOaOA6bpoVPJq4cx6p2Bf3ziy1 Cxq2MLZNxGLCBdeS1DkZn0mGyHBURIWHnCLQ0btPlGNOlZnzyaYT9VPW/OQu5RdFix7Dc0RXTogQH IBB3V460LBUn8Q45WnY+J1Q3lGBz6F6jKloLtFMkD7WC/LgGK05/A8hzoBCBpjLPHT5c3Mw0U7srr H/xKpHrKXntt+gbRGSiDN0+OgoGeStX7aCLBcgA/teKsN2zHvwngUizeIkl/XnuUSb83dudJuXM/U Yp2auE8XLSThvEU+1qm2zC1/mm5fFQeCf6fXSfSx5MLVKQx4EDiAdhxauFekyGDstMPML2Pwmsxzd x/wzh8OnKgOanDrrZjH76iWG0y8FP9EmOVS5YvvAtUxQ5iUN/Vip0sZhvLkTLegINSzsXM2tjCtoY SN08Py+6Fh/RC1HemfH6oZYX3RZIZDhYE8xaLWHcrkTQ5uo5PHgQbBEduq8tKBCE+aZlI9EWsogYM NWEJJY8Af7yhBBVehry+7u1UfLqnObLKrlOEa3mFtDiaalA0WNH7Rw5w+UP/jRvm1pdFmcTHFB7I5 V4OOQpt5q2xjhwSTiY2hnv+4lPFKHCROfuLJouwH8=; From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, qemu-block@nongnu.org, akihiko.odaki@daynix.com Date: Fri, 28 Jun 2024 17:03:34 +0100 Message-Id: <20240628160334.653168-1-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 2a00:23c4:8bb4:4000:71e:fc91:de8e:dcdf X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH v2] hw/ide/macio.c: switch from using qemu_allocate_irq() to qdev input GPIOs X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.ilande.co.uk) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.ilande.co.uk X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1719590668675100003 Content-Type: text/plain; charset="utf-8" This prevents the IRQs from being leaked when the macio IDE device is used. Signed-off-by: Mark Cave-Ayland Reviewed-by: Peter Maydell Reviewed-by: Akihiko Odaki Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/ide/macio.c | 10 ++++++---- include/hw/misc/macio/macio.h | 7 +++++-- 2 files changed, 11 insertions(+), 6 deletions(-) v2: - Delete dma_irq and ide_irq from MACIOIDEState - Add R-B tag from Peter =20 diff --git a/hw/ide/macio.c b/hw/ide/macio.c index aca90d04f0..e84bf2c9f6 100644 --- a/hw/ide/macio.c +++ b/hw/ide/macio.c @@ -420,7 +420,8 @@ static void macio_ide_realizefn(DeviceState *dev, Error= **errp) { MACIOIDEState *s =3D MACIO_IDE(dev); =20 - ide_bus_init_output_irq(&s->bus, s->ide_irq); + ide_bus_init_output_irq(&s->bus, + qdev_get_gpio_in(dev, MACIO_IDE_PMAC_IDE_IRQ)); =20 /* Register DMA callbacks */ s->dma.ops =3D &dbdma_ops; @@ -456,8 +457,8 @@ static void macio_ide_initfn(Object *obj) sysbus_init_mmio(d, &s->mem); sysbus_init_irq(d, &s->real_ide_irq); sysbus_init_irq(d, &s->real_dma_irq); - s->dma_irq =3D qemu_allocate_irq(pmac_ide_irq, s, 0); - s->ide_irq =3D qemu_allocate_irq(pmac_ide_irq, s, 1); + + qdev_init_gpio_in(DEVICE(obj), pmac_ide_irq, MACIO_IDE_PMAC_NIRQS); =20 object_property_add_link(obj, "dbdma", TYPE_MAC_DBDMA, (Object **) &s->dbdma, @@ -508,7 +509,8 @@ void macio_ide_init_drives(MACIOIDEState *s, DriveInfo = **hd_table) =20 void macio_ide_register_dma(MACIOIDEState *s) { - DBDMA_register_channel(s->dbdma, s->channel, s->dma_irq, + DBDMA_register_channel(s->dbdma, s->channel, + qdev_get_gpio_in(DEVICE(s), MACIO_IDE_PMAC_DMA_= IRQ), pmac_ide_transfer, pmac_ide_flush, s); } =20 diff --git a/include/hw/misc/macio/macio.h b/include/hw/misc/macio/macio.h index 2b54da6b31..16aa95b876 100644 --- a/include/hw/misc/macio/macio.h +++ b/include/hw/misc/macio/macio.h @@ -80,8 +80,6 @@ struct MACIOIDEState { uint32_t channel; qemu_irq real_ide_irq; qemu_irq real_dma_irq; - qemu_irq ide_irq; - qemu_irq dma_irq; =20 MemoryRegion mem; IDEBus bus; @@ -92,6 +90,11 @@ struct MACIOIDEState { uint32_t irq_reg; }; =20 +#define MACIO_IDE_PMAC_NIRQS 2 + +#define MACIO_IDE_PMAC_DMA_IRQ 0 +#define MACIO_IDE_PMAC_IDE_IRQ 1 + void macio_ide_init_drives(MACIOIDEState *ide, DriveInfo **hd_table); void macio_ide_register_dma(MACIOIDEState *ide); =20 --=20 2.39.2