We have sent their implementations separately, and we have received few objective
comments except for some ISA extensions order. So, I have put them together
as one patch set to make it easier for merging.

v1->v2:
    1. Fix the isa orders.
    2. Make zimop/zcmop/zama16b/zabha depend on priviledged 1.13
    2. Add review tags.

The v1 patch set is here
    1. zimop/zcmop
        https://mail.gnu.org/archive/html/qemu-riscv/2024-05/msg00207.html
    2. zama16b
        https://mail.gnu.org/archive/html/qemu-riscv/2024-05/msg00212.html
    3. zabha
        https://mail.gnu.org/archive/html/qemu-riscv/2024-05/msg00214.html

LIU Zhiwei (11):
  target/riscv: Add zimop extension
  disas/riscv: Support zimop disassemble
  target/riscv: Add zcmop extension
  disas/riscv: Support zcmop disassemble
  target/riscv: Support Zama16b extension
  target/riscv: Move gen_amo before implement Zabha
  target/riscv: Add AMO instructions for Zabha
  target/riscv: Move gen_cmpxchg before adding amocas.[b|h]
  target/riscv: Add amocas.[b|h] for Zabha
  target/riscv: Enable zabha for max cpu
  disas/riscv: Support zabha disassemble

 disas/riscv.c                               | 183 ++++++++++++++++++++
 target/riscv/cpu.c                          |   8 +
 target/riscv/cpu_cfg.h                      |   4 +
 target/riscv/insn16.decode                  |   1 +
 target/riscv/insn32.decode                  |  33 ++++
 target/riscv/insn_trans/trans_rva.c.inc     |  51 ++----
 target/riscv/insn_trans/trans_rvd.c.inc     |  14 +-
 target/riscv/insn_trans/trans_rvf.c.inc     |  14 +-
 target/riscv/insn_trans/trans_rvi.c.inc     |   6 +
 target/riscv/insn_trans/trans_rvzabha.c.inc | 145 ++++++++++++++++
 target/riscv/insn_trans/trans_rvzacas.c.inc |  13 --
 target/riscv/insn_trans/trans_rvzcmop.c.inc |  29 ++++
 target/riscv/insn_trans/trans_rvzimop.c.inc |  37 ++++
 target/riscv/tcg/tcg-cpu.c                  |   5 +
 target/riscv/translate.c                    |  38 ++++
 15 files changed, 531 insertions(+), 50 deletions(-)
 create mode 100644 target/riscv/insn_trans/trans_rvzabha.c.inc
 create mode 100644 target/riscv/insn_trans/trans_rvzcmop.c.inc
 create mode 100644 target/riscv/insn_trans/trans_rvzimop.c.inc

-- 
2.25.1

Hi LIU,

On Sun, Jun 30, 2024 at 11:05:48AM +0800, LIU Zhiwei wrote:
>We have sent their implementations separately, and we have received few objective
>comments except for some ISA extensions order. So, I have put them together
>as one patch set to make it easier for merging.
>
>v1->v2:
>    1. Fix the isa orders.
>    2. Make zimop/zcmop/zama16b/zabha depend on priviledged 1.13

I didn't realize you started zimop/zcmop upstream efforts already. I had sent
a patch series last friday. And just noticed that you this one on Saturday.
It seems you had sent first set of zimop/zcmop patches in May (which I missed).

Overall my patches and yours look equivalent. Infact, you've added disasm
support as well, so it's a superset. I'll stop my effort to upstream then.

Thanks for working on these.

Otherwise (for zimop/zcmop patches in this series)

Reviewed-by: Deepak Gupta <debug@rivosinc.com>

>    2. Add review tags.
>
>The v1 patch set is here
>    1. zimop/zcmop
>        https://mail.gnu.org/archive/html/qemu-riscv/2024-05/msg00207.html
>    2. zama16b
>        https://mail.gnu.org/archive/html/qemu-riscv/2024-05/msg00212.html
>    3. zabha
>        https://mail.gnu.org/archive/html/qemu-riscv/2024-05/msg00214.html
>
>LIU Zhiwei (11):
>  target/riscv: Add zimop extension
>  disas/riscv: Support zimop disassemble
>  target/riscv: Add zcmop extension
>  disas/riscv: Support zcmop disassemble
>  target/riscv: Support Zama16b extension
>  target/riscv: Move gen_amo before implement Zabha
>  target/riscv: Add AMO instructions for Zabha
>  target/riscv: Move gen_cmpxchg before adding amocas.[b|h]
>  target/riscv: Add amocas.[b|h] for Zabha
>  target/riscv: Enable zabha for max cpu
>  disas/riscv: Support zabha disassemble
>
> disas/riscv.c                               | 183 ++++++++++++++++++++
> target/riscv/cpu.c                          |   8 +
> target/riscv/cpu_cfg.h                      |   4 +
> target/riscv/insn16.decode                  |   1 +
> target/riscv/insn32.decode                  |  33 ++++
> target/riscv/insn_trans/trans_rva.c.inc     |  51 ++----
> target/riscv/insn_trans/trans_rvd.c.inc     |  14 +-
> target/riscv/insn_trans/trans_rvf.c.inc     |  14 +-
> target/riscv/insn_trans/trans_rvi.c.inc     |   6 +
> target/riscv/insn_trans/trans_rvzabha.c.inc | 145 ++++++++++++++++
> target/riscv/insn_trans/trans_rvzacas.c.inc |  13 --
> target/riscv/insn_trans/trans_rvzcmop.c.inc |  29 ++++
> target/riscv/insn_trans/trans_rvzimop.c.inc |  37 ++++
> target/riscv/tcg/tcg-cpu.c                  |   5 +
> target/riscv/translate.c                    |  38 ++++
> 15 files changed, 531 insertions(+), 50 deletions(-)
> create mode 100644 target/riscv/insn_trans/trans_rvzabha.c.inc
> create mode 100644 target/riscv/insn_trans/trans_rvzcmop.c.inc
> create mode 100644 target/riscv/insn_trans/trans_rvzimop.c.inc
>
>-- 
>2.25.1
>
>