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Mon, 01 Jul 2024 04:03:25 -0700 (PDT) Date: Mon, 1 Jul 2024 11:02:30 +0000 In-Reply-To: <20240701110241.2005222-1-smostafa@google.com> Mime-Version: 1.0 References: <20240701110241.2005222-1-smostafa@google.com> X-Mailer: git-send-email 2.45.2.803.g4e1b14247a-goog Message-ID: <20240701110241.2005222-9-smostafa@google.com> Subject: [PATCH v4 08/19] hw/arm/smmuv3: Translate CD and TT using stage-2 table From: Mostafa Saleh To: qemu-arm@nongnu.org, eric.auger@redhat.com, peter.maydell@linaro.org, qemu-devel@nongnu.org Cc: jean-philippe@linaro.org, alex.bennee@linaro.org, maz@kernel.org, nicolinc@nvidia.com, julien@xen.org, richard.henderson@linaro.org, marcin.juszkiewicz@linaro.org, Mostafa Saleh Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::34a; envelope-from=3_YyCZggKClwMGIMN494AIIAF8.6IGK8GO-78P8FHIHAHO.ILA@flex--smostafa.bounces.google.com; helo=mail-wm1-x34a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1719831937950100009 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" According to ARM SMMU architecture specification (ARM IHI 0070 F.b), In "5.2 Stream Table Entry": [51:6] S1ContextPtr If Config[1] =3D=3D 1 (stage 2 enabled), this pointer is an IPA translated= by stage 2 and the programmed value must be within the range of the IAS. In "5.4.1 CD notes": The translation table walks performed from TTB0 or TTB1 are always perform= ed in IPA space if stage 2 translations are enabled. This patch implements translation of the S1 context descriptor pointer and TTBx base addresses through the S2 stage (IPA -> PA) smmuv3_do_translate() is updated to have one arg which is translation class, this is useful to: - Decide wether a translation is stage-2 only or use the STE config. - Populate the class in case of faults, WALK_EABT is left unchanged, as it is always triggered from TT access so no need to use the input class. In case for stage-2 only translation, used in the context of nested translation, the stage and asid are saved and restored before and after calling smmu_translate(). Translating CD or TTBx can fail for the following reasons: 1) Large address size: This is described in (3.4.3 Address sizes of SMMU-originated accesses) - For CD ptr larger than IAS, for SMMUv3.1, it can trigger either C_BAD_STE or Translation fault, we implement the latter as it requires no extra code. - For TTBx, if larger than the effective stage 1 output address size, it triggers C_BAD_CD. 2) Faults from PTWs (7.3 Event records) - F_ADDR_SIZE: large address size after first level causes stage 2 Addre= ss Size fault (Also in 3.4.3 Address sizes of SMMU-originated accesses) - F_PERMISSION: Same as an address translation. However, when CLASS =3D=3D CD, the access is implicitly Data and a read. - F_ACCESS: Same as an address translation. - F_TRANSLATION: Same as an address translation. - F_WALK_EABT: Same as an address translation. These are already implemented in the PTW logic, so no extra handling required. Reviewed-by: Eric Auger Signed-off-by: Mostafa Saleh --- hw/arm/smmuv3.c | 91 +++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 80 insertions(+), 11 deletions(-) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 229b3c388c..86f95c1e40 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -337,14 +337,35 @@ static int smmu_get_ste(SMMUv3State *s, dma_addr_t ad= dr, STE *buf, =20 } =20 +static SMMUTranslationStatus smmuv3_do_translate(SMMUv3State *s, hwaddr ad= dr, + SMMUTransCfg *cfg, + SMMUEventInfo *event, + IOMMUAccessFlags flag, + SMMUTLBEntry **out_entry, + SMMUTranslationClass clas= s); /* @ssid > 0 not supported yet */ -static int smmu_get_cd(SMMUv3State *s, STE *ste, uint32_t ssid, - CD *buf, SMMUEventInfo *event) +static int smmu_get_cd(SMMUv3State *s, STE *ste, SMMUTransCfg *cfg, + uint32_t ssid, CD *buf, SMMUEventInfo *event) { dma_addr_t addr =3D STE_CTXPTR(ste); int ret, i; + SMMUTranslationStatus status; + SMMUTLBEntry *entry; =20 trace_smmuv3_get_cd(addr); + + if (cfg->stage =3D=3D SMMU_NESTED) { + status =3D smmuv3_do_translate(s, addr, cfg, event, + IOMMU_RO, &entry, SMMU_CLASS_CD); + + /* Same PTW faults are reported but with CLASS =3D CD. */ + if (status !=3D SMMU_TRANS_SUCCESS) { + return -EINVAL; + } + + addr =3D CACHED_ENTRY_TO_ADDR(entry, addr); + } + /* TODO: guarantee 64-bit single-copy atomicity */ ret =3D dma_memory_read(&address_space_memory, addr, buf, sizeof(*buf), MEMTXATTRS_UNSPECIFIED); @@ -659,10 +680,13 @@ static int smmu_find_ste(SMMUv3State *s, uint32_t sid= , STE *ste, return 0; } =20 -static int decode_cd(SMMUTransCfg *cfg, CD *cd, SMMUEventInfo *event) +static int decode_cd(SMMUv3State *s, SMMUTransCfg *cfg, + CD *cd, SMMUEventInfo *event) { int ret =3D -EINVAL; int i; + SMMUTranslationStatus status; + SMMUTLBEntry *entry; =20 if (!CD_VALID(cd) || !CD_AARCH64(cd)) { goto bad_cd; @@ -713,9 +737,26 @@ static int decode_cd(SMMUTransCfg *cfg, CD *cd, SMMUEv= entInfo *event) =20 tt->tsz =3D tsz; tt->ttb =3D CD_TTB(cd, i); + if (tt->ttb & ~(MAKE_64BIT_MASK(0, cfg->oas))) { goto bad_cd; } + + /* Translate the TTBx, from IPA to PA if nesting is enabled. */ + if (cfg->stage =3D=3D SMMU_NESTED) { + status =3D smmuv3_do_translate(s, tt->ttb, cfg, event, IOMMU_R= O, + &entry, SMMU_CLASS_TT); + /* + * Same PTW faults are reported but with CLASS =3D TT. + * If TTBx is larger than the effective stage 1 output addres + * size, it reports C_BAD_CD, which is handled by the above ca= se. + */ + if (status !=3D SMMU_TRANS_SUCCESS) { + return -EINVAL; + } + tt->ttb =3D CACHED_ENTRY_TO_ADDR(entry, tt->ttb); + } + tt->had =3D CD_HAD(cd, i); trace_smmuv3_decode_cd_tt(i, tt->tsz, tt->ttb, tt->granule_sz, tt-= >had); } @@ -767,12 +808,12 @@ static int smmuv3_decode_config(IOMMUMemoryRegion *mr= , SMMUTransCfg *cfg, return 0; } =20 - ret =3D smmu_get_cd(s, &ste, 0 /* ssid */, &cd, event); + ret =3D smmu_get_cd(s, &ste, cfg, 0 /* ssid */, &cd, event); if (ret) { return ret; } =20 - return decode_cd(cfg, &cd, event); + return decode_cd(s, cfg, &cd, event); } =20 /** @@ -832,13 +873,40 @@ static SMMUTranslationStatus smmuv3_do_translate(SMMU= v3State *s, hwaddr addr, SMMUTransCfg *cfg, SMMUEventInfo *event, IOMMUAccessFlags flag, - SMMUTLBEntry **out_entry) + SMMUTLBEntry **out_entry, + SMMUTranslationClass clas= s) { SMMUPTWEventInfo ptw_info =3D {}; SMMUState *bs =3D ARM_SMMU(s); SMMUTLBEntry *cached_entry =3D NULL; + int asid, stage; + bool S2_only =3D class !=3D SMMU_CLASS_IN; + + /* + * The function uses the argument class to indentify which stage is us= ed: + * - CLASS =3D IN: Means an input translation, determine the stage fro= m STE. + * - CLASS =3D CD: Means the addr is an IPA of the CD, and it would be + * tranlsated using the stage-2. + * - CLASS =3D TT: Means the addr is an IPA of the stage-1 translation= table + * and it would be tranlsated using the stage-2. + * For the last 2 cases instead of having intrusive changes in the com= mon + * logic, we modify the cfg to be a stage-2 translation only in case of + * nested, and then restore it after. + */ + if (S2_only) { + asid =3D cfg->asid; + stage =3D cfg->stage; + cfg->asid =3D -1; + cfg->stage =3D SMMU_STAGE_2; + } =20 cached_entry =3D smmu_translate(bs, cfg, addr, flag, &ptw_info); + + if (S2_only) { + cfg->asid =3D asid; + cfg->stage =3D stage; + } + if (!cached_entry) { /* All faults from PTW has S2 field. */ event->u.f_walk_eabt.s2 =3D (ptw_info.stage =3D=3D SMMU_STAGE_2); @@ -855,7 +923,7 @@ static SMMUTranslationStatus smmuv3_do_translate(SMMUv3= State *s, hwaddr addr, event->type =3D SMMU_EVT_F_TRANSLATION; event->u.f_translation.addr =3D addr; event->u.f_translation.addr2 =3D ptw_info.addr; - event->u.f_translation.class =3D SMMU_CLASS_IN; + event->u.f_translation.class =3D class; event->u.f_translation.rnw =3D flag & 0x1; } break; @@ -864,7 +932,7 @@ static SMMUTranslationStatus smmuv3_do_translate(SMMUv3= State *s, hwaddr addr, event->type =3D SMMU_EVT_F_ADDR_SIZE; event->u.f_addr_size.addr =3D addr; event->u.f_addr_size.addr2 =3D ptw_info.addr; - event->u.f_addr_size.class =3D SMMU_CLASS_IN; + event->u.f_addr_size.class =3D class; event->u.f_addr_size.rnw =3D flag & 0x1; } break; @@ -873,7 +941,7 @@ static SMMUTranslationStatus smmuv3_do_translate(SMMUv3= State *s, hwaddr addr, event->type =3D SMMU_EVT_F_ACCESS; event->u.f_access.addr =3D addr; event->u.f_access.addr2 =3D ptw_info.addr; - event->u.f_access.class =3D SMMU_CLASS_IN; + event->u.f_access.class =3D class; event->u.f_access.rnw =3D flag & 0x1; } break; @@ -882,7 +950,7 @@ static SMMUTranslationStatus smmuv3_do_translate(SMMUv3= State *s, hwaddr addr, event->type =3D SMMU_EVT_F_PERMISSION; event->u.f_permission.addr =3D addr; event->u.f_permission.addr2 =3D ptw_info.addr; - event->u.f_permission.class =3D SMMU_CLASS_IN; + event->u.f_permission.class =3D class; event->u.f_permission.rnw =3D flag & 0x1; } break; @@ -943,7 +1011,8 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegio= n *mr, hwaddr addr, goto epilogue; } =20 - status =3D smmuv3_do_translate(s, addr, cfg, &event, flag, &cached_ent= ry); + status =3D smmuv3_do_translate(s, addr, cfg, &event, flag, + &cached_entry, SMMU_CLASS_IN); =20 epilogue: qemu_mutex_unlock(&s->mutex); --=20 2.45.2.803.g4e1b14247a-goog