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Wed, 03 Jul 2024 04:01:40 -0700 (PDT) X-Google-Smtp-Source: AGHT+IG8M6Ll8xZf5b1S/x9uPIecJp/J5MAA53yE1gyb1rsoqKUEba/weg/V4byMbHtYu5pq6ER07Q== X-Received: by 2002:a05:600c:4fc5:b0:425:73a8:2fa3 with SMTP id 5b1f17b1804b1-4257a04fe4emr68535995e9.30.1720004499604; Wed, 03 Jul 2024 04:01:39 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: michael.roth@amd.com, zixchen@redhat.com Subject: [RFC PATCH 1/2] target/i386: add support for masking CPUID features in confidential guests Date: Wed, 3 Jul 2024 13:01:33 +0200 Message-ID: <20240703110134.1645979-2-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240703110134.1645979-1-pbonzini@redhat.com> References: <20240703110134.1645979-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1720004550943100007 Content-Type: text/plain; charset="utf-8" Some CPUID features may be provided by KVM for some guests, independent of processor support, for example TSC deadline or TSC adjust. If these are not supported by the confidential computing firmware, however, the guest will fail to start. Add support for removing unsupported features from "-cpu host". Signed-off-by: Paolo Bonzini --- target/i386/confidential-guest.h | 24 ++++++++++++++++++++++++ target/i386/cpu.c | 9 +++++++++ target/i386/kvm/kvm.c | 5 +++++ 3 files changed, 38 insertions(+) diff --git a/target/i386/confidential-guest.h b/target/i386/confidential-gu= est.h index 532e172a60b..7342d2843aa 100644 --- a/target/i386/confidential-guest.h +++ b/target/i386/confidential-guest.h @@ -39,6 +39,8 @@ struct X86ConfidentialGuestClass { =20 /* */ int (*kvm_type)(X86ConfidentialGuest *cg); + uint32_t (*mask_cpuid_features)(X86ConfidentialGuest *cg, uint32_t fea= ture, uint32_t index, + int reg, uint32_t value); }; =20 /** @@ -56,4 +58,26 @@ static inline int x86_confidential_guest_kvm_type(X86Con= fidentialGuest *cg) return 0; } } + +/** + * x86_confidential_guest_mask_cpuid_features: + * + * Removes unsupported features from a confidential guest's CPUID values, = returns + * the value with the bits removed. The bits removed should be those that= KVM + * provides independent of host-supported CPUID features, but are not supp= orted by + * the confidential computing firmware. + */ +static inline int x86_confidential_guest_mask_cpuid_features(X86Confidenti= alGuest *cg, + uint32_t feat= ure, uint32_t index, + int reg, uint= 32_t value) +{ + X86ConfidentialGuestClass *klass =3D X86_CONFIDENTIAL_GUEST_GET_CLASS(= cg); + + if (klass->mask_cpuid_features) { + return klass->mask_cpuid_features(cg, feature, index, reg, value); + } else { + return value; + } +} + #endif diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index dd8b0f33136..056d117cd11 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -548,6 +548,11 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uin= t32_t function, ret |=3D 1U << KVM_HINTS_REALTIME; } =20 + if (current_machine->cgs) { + ret =3D x86_confidential_guest_mask_cpuid_features( + X86_CONFIDENTIAL_GUEST(current_machine->cgs), + function, index, reg, ret); + } return ret; } =20 --=20 2.45.2 From nobody Sun Dec 29 01:08:39 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1720004548; cv=none; d=zohomail.com; s=zohoarc; b=UUW0sZn7rNtqrpQHv9rVDCqfwrbHOKDQVyodz1oY+GXXcf0SaqZI5Bdmxx/+YSNsPF7KPnedk066bt2tQ6lgbyk9jJPeGQiXvXy8pnHKBDmKaca4SUa2BV+ZzhZtdKgYj5CqCo2OQWIaYpb0hl+IO+y9bXuxKm3/7BBeadxdKV4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1720004548; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=DJXfkX2FVeuW09rGLHMQl8eKx+VVtzqs987bhwWwkiQ=; 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Wed, 03 Jul 2024 04:01:43 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHlQf9oE25QGcbnA3VpzOI0PgFwfWC+U1jiauh9etXVXjtyuBzmohs8+ZWksv+fO9Qw2qN7/A== X-Received: by 2002:a05:600c:291:b0:425:641c:5f40 with SMTP id 5b1f17b1804b1-4257a027077mr87747835e9.39.1720004503243; Wed, 03 Jul 2024 04:01:43 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: michael.roth@amd.com, zixchen@redhat.com Subject: [RFC PATCH 2/2] target/i386/SEV: implement mask_cpuid_features Date: Wed, 3 Jul 2024 13:01:34 +0200 Message-ID: <20240703110134.1645979-3-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240703110134.1645979-1-pbonzini@redhat.com> References: <20240703110134.1645979-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1720004548869100001 Content-Type: text/plain; charset="utf-8" SNP firmware rejects several features that KVM implements without needing hardware support. If these are specified, for example with "-cpu host", the guest will fail to start. I am marking this as RFC because it's not future proof. If in the future AMD processors do provide any of these bits, this is going to break (tsc_deadline and tsc_adjust are the most likely one). Including the bits if they are present in host CPUID is not super safe either, since the firmware might not be updated to follow suit. Reported-by: Zixi Chen Not-quite-signed-off-by: Paolo Bonzini --- target/i386/cpu.h | 4 ++++ target/i386/sev.c | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 37 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 9bea7142bf4..31c9b43849e 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -812,6 +812,8 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu= , FeatureWord w); =20 /* Support RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */ #define CPUID_7_0_EBX_FSGSBASE (1U << 0) +/* Support TSC adjust MSR */ +#define CPUID_7_0_EBX_TSC_ADJUST (1U << 1) /* Support SGX */ #define CPUID_7_0_EBX_SGX (1U << 2) /* 1st Group of Advanced Bit Manipulation Extensions */ @@ -1002,6 +1004,8 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *c= pu, FeatureWord w); #define CPUID_8000_0008_EBX_STIBP_ALWAYS_ON (1U << 17) /* Speculative Store Bypass Disable */ #define CPUID_8000_0008_EBX_AMD_SSBD (1U << 24) +/* Paravirtualized Speculative Store Bypass Disable MSR */ +#define CPUID_8000_0008_EBX_VIRT_SSBD (1U << 25) /* Predictive Store Forwarding Disable */ #define CPUID_8000_0008_EBX_AMD_PSFD (1U << 28) =20 diff --git a/target/i386/sev.c b/target/i386/sev.c index 2a0f94d390d..280eaef8723 100644 --- a/target/i386/sev.c +++ b/target/i386/sev.c @@ -945,6 +945,38 @@ out: return ret; } =20 +static uint32_t +sev_snp_mask_cpuid_features(X86ConfidentialGuest *cg, uint32_t feature, ui= nt32_t index, + int reg, uint32_t value) +{ + switch (feature) { + case 1: + if (reg =3D=3D R_ECX) { + return value & ~CPUID_EXT_TSC_DEADLINE_TIMER; + } + break; + case 7: + if (index =3D=3D 0 && reg =3D=3D R_EBX) { + return value & ~CPUID_7_0_EBX_TSC_ADJUST; + } + if (index =3D=3D 0 && reg =3D=3D R_EDX) { + return value & ~(CPUID_7_0_EDX_SPEC_CTRL | + CPUID_7_0_EDX_STIBP | + CPUID_7_0_EDX_FLUSH_L1D | + CPUID_7_0_EDX_ARCH_CAPABILITIES | + CPUID_7_0_EDX_CORE_CAPABILITY | + CPUID_7_0_EDX_SPEC_CTRL_SSBD); + } + break; + case 0x80000008: + if (reg =3D=3D R_EBX) { + return value & ~CPUID_8000_0008_EBX_VIRT_SSBD; + } + break; + } + return value; +} + static int sev_launch_update_data(SevCommonState *sev_common, hwaddr gpa, uint8_t *addr, size_t len) @@ -2315,6 +2347,7 @@ sev_snp_guest_class_init(ObjectClass *oc, void *data) klass->launch_finish =3D sev_snp_launch_finish; klass->launch_update_data =3D sev_snp_launch_update_data; klass->kvm_init =3D sev_snp_kvm_init; + x86_klass->mask_cpuid_features =3D sev_snp_mask_cpuid_features; x86_klass->kvm_type =3D sev_snp_kvm_type; =20 object_class_property_add(oc, "policy", "uint64", --=20 2.45.2