From nobody Sun Dec 29 01:01:36 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.alibaba.com ARC-Seal: i=1; a=rsa-sha256; t=1720010275; cv=none; d=zohomail.com; s=zohoarc; b=aA2F1L/ExZ0eDnL5ChLDM2xrm1fF05Dck5DVyhtOMoZwLveR8VdLkav6Euqv4IKWRxbFI3jdeCvu0OUhXZ1sHUCr+ytv6E9RpfTHyp5kPgDVPdiRaob2EEYKkDnF8WNeNJ+xnLVQrNc78FPv3cgp5bam8haZCXdfbAoHL05APLU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1720010275; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=O0IOyE9TbdMdefydvuFeYIhe0/fmQANDiIgHaap1df0=; b=EFYncRBuz61xumQDyTjI7ntRHuAK0M8KMgqFJuLDYdKFEOi4EAycKwyx331n11SIesPkvkAnJjfFnP83CH8DDG6qh0KTRrw0LYSV3D7QW/ddI2DNGdFLPf6+7AnTBpDFuWA4YGp5Wu2mIiGa4q1YfU4bpndH30ZwCRMKDwf1aeY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 172001027550268.28667294573256; Wed, 3 Jul 2024 05:37:55 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sOzEu-0002GC-PW; Wed, 03 Jul 2024 08:37:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sOzEb-0001sK-K6; Wed, 03 Jul 2024 08:37:17 -0400 Received: from out30-101.freemail.mail.aliyun.com ([115.124.30.101]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sOzEH-0002UI-75; Wed, 03 Jul 2024 08:37:16 -0400 Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@linux.alibaba.com fp:SMTPD_---0W9nPEZ0_1720010207) by smtp.aliyun-inc.com; Wed, 03 Jul 2024 20:36:48 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1720010211; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=O0IOyE9TbdMdefydvuFeYIhe0/fmQANDiIgHaap1df0=; b=C0hJqFOTcwBYfmstDJQfzgnPqhbVTRq61J6lrq8FxqxJGbn1BJqObRWG167PdCaGzWXahdsvL+XFQtrS7wJYkViZYZ2zdgIhpSG5RlzqFV/nfOGVGBoVsUbAvNxftJRF1ZEZrdv6aqfsvL5Y5EVbTtnvnnB9X4+lARZ52iyZYDw= X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R201e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=maildocker-contentspam033045220184; MF=zhiwei_liu@linux.alibaba.com; NM=1; PH=DS; RN=9; SR=0; TI=SMTPD_---0W9nPEZ0_1720010207; From: LIU Zhiwei To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, zhiwei_liu@linux.alibaba.com, TANG Tiancheng Subject: [PATCH v2 1/7] target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI Date: Wed, 3 Jul 2024 20:34:43 +0800 Message-Id: <20240703123449.1108-2-zhiwei_liu@linux.alibaba.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20240703123449.1108-1-zhiwei_liu@linux.alibaba.com> References: <20240703123449.1108-1-zhiwei_liu@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=115.124.30.101; envelope-from=zhiwei_liu@linux.alibaba.com; helo=out30-101.freemail.mail.aliyun.com X-Spam_score_int: -174 X-Spam_score: -17.5 X-Spam_bar: ----------------- X-Spam_report: (-17.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.alibaba.com) X-ZM-MESSAGEID: 1720010275990100001 Content-Type: text/plain; charset="utf-8" From: TANG Tiancheng RV32 OpenSBI need a fw_dynamic_info parameter with 32-bit fields instead of target_ulong. In RV64 QEMU, target_ulong is 64. So it is not right for booting RV32 OpenS= BI. We create a fw_dynmaic_info32 struct for this purpose. Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Alistair Francis --- hw/riscv/boot.c | 35 ++++++++++++++++++++++----------- hw/riscv/sifive_u.c | 3 ++- include/hw/riscv/boot.h | 4 +++- include/hw/riscv/boot_opensbi.h | 29 +++++++++++++++++++++++++++ 4 files changed, 57 insertions(+), 14 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 47281ca853..1a2c1ff9e0 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -342,27 +342,33 @@ void riscv_load_fdt(hwaddr fdt_addr, void *fdt) rom_ptr_for_as(&address_space_memory, fdt_addr, fd= tsize)); } =20 -void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base, - hwaddr rom_size, uint32_t reset_vec_size, +void riscv_rom_copy_firmware_info(MachineState *machine, + RISCVHartArrayState *harts, + hwaddr rom_base, hwaddr rom_size, + uint32_t reset_vec_size, uint64_t kernel_entry) { + struct fw_dynamic_info32 dinfo32; struct fw_dynamic_info dinfo; size_t dinfo_len; =20 - if (sizeof(dinfo.magic) =3D=3D 4) { - dinfo.magic =3D cpu_to_le32(FW_DYNAMIC_INFO_MAGIC_VALUE); - dinfo.version =3D cpu_to_le32(FW_DYNAMIC_INFO_VERSION); - dinfo.next_mode =3D cpu_to_le32(FW_DYNAMIC_INFO_NEXT_MODE_S); - dinfo.next_addr =3D cpu_to_le32(kernel_entry); + if (riscv_is_32bit(harts)) { + dinfo32.magic =3D cpu_to_le32(FW_DYNAMIC_INFO_MAGIC_VALUE); + dinfo32.version =3D cpu_to_le32(FW_DYNAMIC_INFO_VERSION); + dinfo32.next_mode =3D cpu_to_le32(FW_DYNAMIC_INFO_NEXT_MODE_S); + dinfo32.next_addr =3D cpu_to_le32(kernel_entry); + dinfo32.options =3D 0; + dinfo32.boot_hart =3D 0; + dinfo_len =3D sizeof(dinfo32); } else { dinfo.magic =3D cpu_to_le64(FW_DYNAMIC_INFO_MAGIC_VALUE); dinfo.version =3D cpu_to_le64(FW_DYNAMIC_INFO_VERSION); dinfo.next_mode =3D cpu_to_le64(FW_DYNAMIC_INFO_NEXT_MODE_S); dinfo.next_addr =3D cpu_to_le64(kernel_entry); + dinfo.options =3D 0; + dinfo.boot_hart =3D 0; + dinfo_len =3D sizeof(dinfo); } - dinfo.options =3D 0; - dinfo.boot_hart =3D 0; - dinfo_len =3D sizeof(dinfo); =20 /** * copy the dynamic firmware info. This information is specific to @@ -374,7 +380,10 @@ void riscv_rom_copy_firmware_info(MachineState *machin= e, hwaddr rom_base, exit(1); } =20 - rom_add_blob_fixed_as("mrom.finfo", &dinfo, dinfo_len, + rom_add_blob_fixed_as("mrom.finfo", + riscv_is_32bit(harts) ? + (void *)&dinfo32 : (void *)&dinfo, + dinfo_len, rom_base + reset_vec_size, &address_space_memory); } @@ -430,7 +439,9 @@ void riscv_setup_rom_reset_vec(MachineState *machine, R= ISCVHartArrayState *harts } rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), rom_base, &address_space_memory); - riscv_rom_copy_firmware_info(machine, rom_base, rom_size, sizeof(reset= _vec), + riscv_rom_copy_firmware_info(machine, harts, + rom_base, rom_size, + sizeof(reset_vec), kernel_entry); } =20 diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index af5f923f54..5010c3eadb 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -646,7 +646,8 @@ static void sifive_u_machine_init(MachineState *machine) rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), memmap[SIFIVE_U_DEV_MROM].base, &address_space_m= emory); =20 - riscv_rom_copy_firmware_info(machine, memmap[SIFIVE_U_DEV_MROM].base, + riscv_rom_copy_firmware_info(machine, &s->soc.u_cpus, + memmap[SIFIVE_U_DEV_MROM].base, memmap[SIFIVE_U_DEV_MROM].size, sizeof(reset_vec), kernel_entry); =20 diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index a2e4ae9cb0..806256d23f 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -56,7 +56,9 @@ void riscv_setup_rom_reset_vec(MachineState *machine, RIS= CVHartArrayState *harts hwaddr rom_base, hwaddr rom_size, uint64_t kernel_entry, uint64_t fdt_load_addr); -void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base, +void riscv_rom_copy_firmware_info(MachineState *machine, + RISCVHartArrayState *harts, + hwaddr rom_base, hwaddr rom_size, uint32_t reset_vec_size, uint64_t kernel_entry); diff --git a/include/hw/riscv/boot_opensbi.h b/include/hw/riscv/boot_opensb= i.h index 1b749663dc..18664a174b 100644 --- a/include/hw/riscv/boot_opensbi.h +++ b/include/hw/riscv/boot_opensbi.h @@ -58,4 +58,33 @@ struct fw_dynamic_info { target_long boot_hart; }; =20 +/** Representation dynamic info passed by previous booting stage */ +struct fw_dynamic_info32 { + /** Info magic */ + int32_t magic; + /** Info version */ + int32_t version; + /** Next booting stage address */ + int32_t next_addr; + /** Next booting stage mode */ + int32_t next_mode; + /** Options for OpenSBI library */ + int32_t options; + /** + * Preferred boot HART id + * + * It is possible that the previous booting stage uses same link + * address as the FW_DYNAMIC firmware. In this case, the relocation + * lottery mechanism can potentially overwrite the previous booting + * stage while other HARTs are still running in the previous booting + * stage leading to boot-time crash. To avoid this boot-time crash, + * the previous booting stage can specify last HART that will jump + * to the FW_DYNAMIC firmware as the preferred boot HART. + * + * To avoid specifying a preferred boot HART, the previous booting + * stage can set it to -1UL which will force the FW_DYNAMIC firmware + * to use the relocation lottery mechanism. + */ + int32_t boot_hart; +}; #endif --=20 2.43.0 From nobody Sun Dec 29 01:01:36 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.alibaba.com ARC-Seal: i=1; a=rsa-sha256; t=1720010276; cv=none; d=zohomail.com; s=zohoarc; b=gSomeRI137/gFbIfJPkdnyP0Awlu3hlPAfVYT6ChakWdbx2oq+A4Ilg7SEhuvCUqhi/aEZIooOx0zuU01hKTIfbOl+Mk75KH4VNTUbT0Xb/VFM8KPbwBmqUUEdDljq/qGgDznbNFNm7MEVaKi2/J7OXKMrBnkRqGwCEWyGymlvE= ARC-Message-Signature: i=1; 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Wed, 03 Jul 2024 08:37:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sOzEo-00028a-MY; Wed, 03 Jul 2024 08:37:32 -0400 Received: from out30-124.freemail.mail.aliyun.com ([115.124.30.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sOzEm-00038u-Bi; Wed, 03 Jul 2024 08:37:30 -0400 Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@linux.alibaba.com fp:SMTPD_---0W9n0mAf_1720010238) by smtp.aliyun-inc.com; Wed, 03 Jul 2024 20:37:19 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1720010241; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=yP4xGUg/jtJYMbv4Nnc5KcfpDh6fhiLkblxWBoCloKw=; b=LiD364o+VgIgiKZ6UeEzMCy4vvskOS0EUc2SuLImhkyO35mL84WNnboZ2ER+r3zTIxmg6/nd6nvBO+i4uHOL6tCm+vVprqTyCjJfarimIY3NUvj4zRTte73XvVyg+rI+KJ9JvxP4gPAC5i3QzUiy5ik25PCakEVvR5VazESoc2o= X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R171e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=maildocker-contentspam033045220184; MF=zhiwei_liu@linux.alibaba.com; NM=1; PH=DS; RN=9; SR=0; TI=SMTPD_---0W9n0mAf_1720010238; From: LIU Zhiwei To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, zhiwei_liu@linux.alibaba.com, TANG Tiancheng Subject: [PATCH v2 2/7] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32 Date: Wed, 3 Jul 2024 20:34:44 +0800 Message-Id: <20240703123449.1108-3-zhiwei_liu@linux.alibaba.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20240703123449.1108-1-zhiwei_liu@linux.alibaba.com> References: <20240703123449.1108-1-zhiwei_liu@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=115.124.30.124; envelope-from=zhiwei_liu@linux.alibaba.com; helo=out30-124.freemail.mail.aliyun.com X-Spam_score_int: -174 X-Spam_score: -17.5 X-Spam_bar: ----------------- X-Spam_report: (-17.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.alibaba.com) X-ZM-MESSAGEID: 1720010277979100007 Content-Type: text/plain; charset="utf-8" From: TANG Tiancheng Ensure pmp_size is correctly determined using mxl for RV32 in RV64 QEMU. Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Alistair Francis --- target/riscv/pmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 9eea397e72..f65aa3dba7 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -326,7 +326,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, hwaddr addr, */ pmp_size =3D -(addr | TARGET_PAGE_MASK); } else { - pmp_size =3D sizeof(target_ulong); + pmp_size =3D 2UL << riscv_cpu_mxl(env); } } else { pmp_size =3D size; --=20 2.43.0 From nobody Sun Dec 29 01:01:36 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.alibaba.com ARC-Seal: i=1; a=rsa-sha256; t=1720010291; cv=none; d=zohomail.com; s=zohoarc; b=N/8I59BbAueDlkSHMKkhgrkIPAmwO44n1oV3AQRczrAxDsi/qmHP48C38lXD5YpxkgsoFeOMHeukMlLT1QCbDAx9HhUqZoWfpl20OAA5o827/YMjJ20CO4Io5z8hOiVcjuUqo3pjT/BpJZliSt/43fg1Q2+Yni+qR5wEMsdUVnw= ARC-Message-Signature: i=1; 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Wed, 03 Jul 2024 08:38:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sOzFG-0003E8-F3; Wed, 03 Jul 2024 08:37:58 -0400 Received: from out30-133.freemail.mail.aliyun.com ([115.124.30.133]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sOzFE-0003Gd-2N; Wed, 03 Jul 2024 08:37:57 -0400 Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@linux.alibaba.com fp:SMTPD_---0W9mSYbB_1720010270) by smtp.aliyun-inc.com; Wed, 03 Jul 2024 20:37:50 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1720010271; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=YdcEoj8CgB8O7irbZwmmxqh8LZ3/lGEiuMTR/UhVTBY=; b=spFJ+uvpS4nQMMyDLNt9ElA7csmc5u9JOoIjm9tuAkPyiNjWZcFu/3X5Pro0aZklx/wltseBz/pmT4+bd8k4TN6CBxD9HSZv+qsvRy4sew07KhQBWldSPU5Thy7Ci5D/1nrUEABZxzkrWmF5EcHJPzuCvt7Sdhh393TCghPHNT8= X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R161e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=maildocker-contentspam033023225041; MF=zhiwei_liu@linux.alibaba.com; NM=1; PH=DS; RN=9; SR=0; TI=SMTPD_---0W9mSYbB_1720010270; From: LIU Zhiwei To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, zhiwei_liu@linux.alibaba.com, TANG Tiancheng Subject: [PATCH v2 3/7] target/riscv: Correct SXL return value for RV32 in RV64 QEMU Date: Wed, 3 Jul 2024 20:34:45 +0800 Message-Id: <20240703123449.1108-4-zhiwei_liu@linux.alibaba.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20240703123449.1108-1-zhiwei_liu@linux.alibaba.com> References: <20240703123449.1108-1-zhiwei_liu@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=115.124.30.133; envelope-from=zhiwei_liu@linux.alibaba.com; helo=out30-133.freemail.mail.aliyun.com X-Spam_score_int: -174 X-Spam_score: -17.5 X-Spam_bar: ----------------- X-Spam_report: (-17.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.alibaba.com) X-ZM-MESSAGEID: 1720010292318100001 Content-Type: text/plain; charset="utf-8" From: TANG Tiancheng Ensure that riscv_cpu_sxl returns MXL_RV32 when runningRV32 in an RV64 QEMU. Signed-off-by: TANG Tiancheng Fixes: 05e6ca5e156 ("target/riscv: Ignore reserved bits in PTE for RV64") Reviewed-by: Liu Zhiwei --- target/riscv/cpu.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 6fe0d712b4..36a712044a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -668,8 +668,11 @@ static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *en= v) #ifdef CONFIG_USER_ONLY return env->misa_mxl; #else - return get_field(env->mstatus, MSTATUS64_SXL); + if (env->misa_mxl !=3D MXL_RV32) { + return get_field(env->mstatus, MSTATUS64_SXL); + } #endif + return MXL_RV32; } #endif =20 --=20 2.43.0 From nobody Sun Dec 29 01:01:36 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.alibaba.com ARC-Seal: i=1; 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a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1720010303; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=h9OmjPFJswUW3FYItMhv6mcvZBXG+yLjCEagI6O4X50=; b=pjecgaTPHSZ/m1fBNmsMXEDXXW+5LKaibMBYf6o2IgOhaCqCdqgMa5CDsoJDr8q6IF0bSPPWCuqVhIlFVg7CjPC/Kz/dQ+3DIog4O+8TYHpxDs5W77/fgJ9AwLEs5L1YFq82paZ8kc2KDgJ5ffts13a7XhRpVrxP2g5182iNo6I= X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R971e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=maildocker-contentspam033032014031; MF=zhiwei_liu@linux.alibaba.com; NM=1; PH=DS; RN=9; SR=0; TI=SMTPD_---0W9nPEzQ_1720010301; From: LIU Zhiwei To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, zhiwei_liu@linux.alibaba.com, TANG Tiancheng Subject: [PATCH v2 4/7] target/riscv: Detect sxl to set bit width for RV32 in RV64 Date: Wed, 3 Jul 2024 20:34:46 +0800 Message-Id: <20240703123449.1108-5-zhiwei_liu@linux.alibaba.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20240703123449.1108-1-zhiwei_liu@linux.alibaba.com> References: <20240703123449.1108-1-zhiwei_liu@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: TANG Tiancheng Ensure correct bit width based on sxl when running RV32 on RV64 QEMU. This is required as MMU address translations run in S-mode. Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- target/riscv/cpu_helper.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 6709622dd3..fa3b845c85 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -887,12 +887,14 @@ static int get_physical_address(CPURISCVState *env, h= waddr *physical, =20 CPUState *cs =3D env_cpu(env); int va_bits =3D PGSHIFT + levels * ptidxbits + widened; + int sxlen =3D 16UL << riscv_cpu_sxl(env); + int sxlen_bytes =3D sxlen / 8; =20 if (first_stage =3D=3D true) { target_ulong mask, masked_msbs; =20 - if (TARGET_LONG_BITS > (va_bits - 1)) { - mask =3D (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1; + if (sxlen > (va_bits - 1)) { + mask =3D (1L << (sxlen - (va_bits - 1))) - 1; } else { mask =3D 0; } @@ -961,7 +963,7 @@ restart: =20 int pmp_prot; int pmp_ret =3D get_physical_address_pmp(env, &pmp_prot, pte_addr, - sizeof(target_ulong), + sxlen_bytes, MMU_DATA_LOAD, PRV_S); if (pmp_ret !=3D TRANSLATE_SUCCESS) { return TRANSLATE_PMP_FAIL; @@ -1113,7 +1115,7 @@ restart: * it is no longer valid and we must re-walk the page table. */ MemoryRegion *mr; - hwaddr l =3D sizeof(target_ulong), addr1; + hwaddr l =3D sxlen_bytes, addr1; mr =3D address_space_translate(cs->as, pte_addr, &addr1, &l, false, MEMTXATTRS_UNSPECIFIED); if (memory_region_is_ram(mr)) { @@ -1125,7 +1127,12 @@ restart: */ *pte_pa =3D pte =3D updated_pte; #else - target_ulong old_pte =3D qatomic_cmpxchg(pte_pa, pte, updated_= pte); + target_ulong old_pte; + if (riscv_cpu_sxl(env) =3D=3D MXL_RV32) { + old_pte =3D qatomic_cmpxchg((uint32_t *)pte_pa, pte, updat= ed_pte); + } else { + old_pte =3D qatomic_cmpxchg(pte_pa, pte, updated_pte); + } if (old_pte !=3D pte) { goto restart; } --=20 2.43.0 From nobody Sun Dec 29 01:01:36 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; 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a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1720010333; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=HlD0TJhvV/oGSsh846wGF2BqMkqdDccs6tjMHqvu7Qk=; b=tsxx+IA5e6YaqHvDSlTD0b9FPvN75UuBfatg0K1C1KttTvzyUXbnYmZJS9u9z/YyPOsOvwqEHYZ7TBiJ9+YskvIH34avKomXgeQDsS/FlAunpuoJNUCPGZNDrRgoS7F9aQsaeKuhFg8X3PRvJhwNr83EyK+CdSQj/hTiVxUcLmI= X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R171e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=maildocker-contentspam033037067113; MF=zhiwei_liu@linux.alibaba.com; NM=1; PH=DS; RN=9; SR=0; TI=SMTPD_---0W9nRtcx_1720010332; From: LIU Zhiwei To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, zhiwei_liu@linux.alibaba.com, TANG Tiancheng Subject: [PATCH v2 5/7] target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU Date: Wed, 3 Jul 2024 20:34:47 +0800 Message-Id: <20240703123449.1108-6-zhiwei_liu@linux.alibaba.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20240703123449.1108-1-zhiwei_liu@linux.alibaba.com> References: <20240703123449.1108-1-zhiwei_liu@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: TANG Tiancheng Ensure mcause high bit is correctly set by using 32-bit width for RV32 mode and 64-bit width for RV64 mode. Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- target/riscv/cpu_helper.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index fa3b845c85..a79a03c7e0 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1673,6 +1673,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) target_ulong tinst =3D 0; target_ulong htval =3D 0; target_ulong mtval2 =3D 0; + int sxlen =3D 0; + int mxlen =3D 0; =20 if (!async) { /* set tval to badaddr for traps with address information */ @@ -1799,7 +1801,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) s =3D set_field(s, MSTATUS_SPP, env->priv); s =3D set_field(s, MSTATUS_SIE, 0); env->mstatus =3D s; - env->scause =3D cause | ((target_ulong)async << (TARGET_LONG_BITS = - 1)); + sxlen =3D 16UL << riscv_cpu_sxl(env); + env->scause =3D cause | ((target_ulong)async << (sxlen - 1)); env->sepc =3D env->pc; env->stval =3D tval; env->htval =3D htval; @@ -1830,7 +1833,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) s =3D set_field(s, MSTATUS_MPP, env->priv); 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Wed, 03 Jul 2024 08:39:31 -0400 Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@linux.alibaba.com fp:SMTPD_---0W9nPFGt_1720010363) by smtp.aliyun-inc.com; Wed, 03 Jul 2024 20:39:24 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1720010365; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=pFmkkF8L8S//h49pBMaqQ+MUSB6WVWFO6cwt6uFHPNY=; b=O6I48E27s9gseC6vbA5N1mUTIvJ9Nvt+VUz4RC00X6bPmgbO9mp93y2FZMprTStjjBz8B2fpQIUIIKIO+HGxzOoBo6KNdkQ0helEoAC7ECRhxkq2d9JQhaLkUtzG9uJw7C6NhqSG97K/VHjlcDdKkPy3AQ9AxwBdCsfsMGrVdmY= X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R651e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=maildocker-contentspam033037067111; MF=zhiwei_liu@linux.alibaba.com; NM=1; PH=DS; RN=9; SR=0; TI=SMTPD_---0W9nPFGt_1720010363; From: LIU Zhiwei To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, zhiwei_liu@linux.alibaba.com, TANG Tiancheng Subject: [PATCH v2 6/7] target/riscv: Enable RV32 CPU support in RV64 QEMU Date: Wed, 3 Jul 2024 20:34:48 +0800 Message-Id: <20240703123449.1108-7-zhiwei_liu@linux.alibaba.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20240703123449.1108-1-zhiwei_liu@linux.alibaba.com> References: <20240703123449.1108-1-zhiwei_liu@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: TANG Tiancheng Add gdb XML files and adjust CPU initialization to allow running RV32 CPUs in RV64 QEMU. Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- configs/targets/riscv64-softmmu.mak | 2 +- target/riscv/cpu.c | 17 +++++++++++++---- 2 files changed, 14 insertions(+), 5 deletions(-) diff --git a/configs/targets/riscv64-softmmu.mak b/configs/targets/riscv64-= softmmu.mak index f688ffa7bc..5c1abb4b51 100644 --- a/configs/targets/riscv64-softmmu.mak +++ b/configs/targets/riscv64-softmmu.mak @@ -1,6 +1,6 @@ TARGET_ARCH=3Driscv64 TARGET_BASE_ARCH=3Driscv TARGET_SUPPORTS_MTTCG=3Dy -TARGET_XML_FILES=3D gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xm= l gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-virtual.xml +TARGET_XML_FILES=3D gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xm= l gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-virtual.xml gdb-xml/riscv= -32bit-cpu.xml gdb-xml/riscv-32bit-virtual.xml # needed by boot.c TARGET_NEED_FDT=3Dy diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 69a08e8c2c..58165901a2 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -630,8 +630,10 @@ static void rv64e_bare_cpu_init(Object *obj) riscv_cpu_set_misa_ext(env, RVE); } =20 -#else /* !TARGET_RISCV64 */ +#endif /* !TARGET_RISCV64 */ =20 +#if defined(TARGET_RISCV32) || \ + (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY)) static void rv32_base_cpu_init(Object *obj) { RISCVCPU *cpu =3D RISCV_CPU(obj); @@ -2544,6 +2546,13 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { #if defined(TARGET_RISCV32) DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, MXL_RV32, riscv_any_cpu_= init), DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, MXL_RV32, riscv_max_cpu_= init), +#elif defined(TARGET_RISCV64) + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, MXL_RV64, riscv_any_cpu_= init), + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, MXL_RV64, riscv_max_cpu_= init), +#endif + +#if defined(TARGET_RISCV32) || \ + (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY)) DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, MXL_RV32, rv32_base_cpu_= init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_IBEX, MXL_RV32, rv32_ibex_cpu_= init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E31, MXL_RV32, rv32_sifive_e_= cpu_init), @@ -2551,9 +2560,9 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U34, MXL_RV32, rv32_sifive_u_= cpu_init), DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV32I, MXL_RV32, rv32i_bare_cpu= _init), DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV32E, MXL_RV32, rv32e_bare_cpu= _init), -#elif defined(TARGET_RISCV64) - DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, MXL_RV64, riscv_any_cpu_= init), - DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, MXL_RV64, riscv_max_cpu_= init), +#endif + +#if defined(TARGET_RISCV64) DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, MXL_RV64, rv64_base_cpu_= init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E51, MXL_RV64, rv64_sifive_e_= cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U54, MXL_RV64, rv64_sifive_u_= cpu_init), --=20 2.43.0 From nobody Sun Dec 29 01:01:37 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 03 Jul 2024 20:39:55 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1720010396; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=rTLRqFdMD4b7OWC1tQsY7AZTS4HIoPyqg3r8Of9GuTc=; b=fMckGef08IN4D7tpnndGgxECkA1MXVjBQKID5iMeKswUEw9tKaNtrrPx6IZJWnuUF14KtVcz3h0ogX0zD8d9uR/+N7w1cop5tdTlasrjnBKJMbxc8bVMQlODMLNpzQII4oNhD8IpqlZg2y3dxIVCp3ymSZIXKL3o4Z5Z2h9l+YA= X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R151e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=maildocker-contentspam033032014031; MF=zhiwei_liu@linux.alibaba.com; NM=1; PH=DS; RN=9; SR=0; TI=SMTPD_---0W9nRtuf_1720010394; From: LIU Zhiwei To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, zhiwei_liu@linux.alibaba.com, TANG Tiancheng Subject: [PATCH v2 7/7] tests/avocado: Add an avocado test for riscv64 Date: Wed, 3 Jul 2024 20:34:49 +0800 Message-Id: <20240703123449.1108-8-zhiwei_liu@linux.alibaba.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20240703123449.1108-1-zhiwei_liu@linux.alibaba.com> References: <20240703123449.1108-1-zhiwei_liu@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: TANG Tiancheng To regularly test booting Linux with rv32 on QEMU RV64, we have added a test to boot_linux_console.py to retrieve cpuinfo and verify if it shows 'rv32' when using RV64 to boot rv32 CPUs. Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tests/avocado/boot_linux_console.py | 35 +++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux= _console.py index c35fc5e9ba..408f936f9a 100644 --- a/tests/avocado/boot_linux_console.py +++ b/tests/avocado/boot_linux_console.py @@ -12,6 +12,7 @@ import lzma import gzip import shutil +import time =20 from avocado import skip from avocado import skipUnless @@ -1545,3 +1546,37 @@ def test_xtensa_lx60(self): """ tar_hash =3D '49e88d9933742f0164b60839886c9739cb7a0d34' self.do_test_advcal_2018('02', tar_hash, 'santas-sleigh-ride.elf') + + def test_riscv64_virt_rv32i(self): + """ + :avocado: tags=3Darch:riscv64 + :avocado: tags=3Dmachine:virt + :avocado: tags=3Dcpu:rv32 + """ + kernel_url =3D ('https://github.com/romanheros/rv32-linux/raw/mast= er/Image32.xz') + kernel_hash =3D 'a7ced5c38722481e0821b7cd70719cf53e46c13b' + kernel_path_xz =3D self.fetch_asset(kernel_url, asset_hash=3Dkerne= l_hash) + + kernel_path =3D os.path.join(self.workdir, 'kernel.riscv32') + archive.lzma_uncompress(kernel_path_xz, kernel_path) + + rootfs_url =3D ('https://github.com/romanheros/rv32-linux/raw/mast= er/rootfs.ext2.xz') + rootfs_hash =3D 'dc25ab9d4b233e8e0bcf7eb220d56fd2008fe263' + rootfs_path_xz =3D self.fetch_asset(rootfs_url, asset_hash=3Drootf= s_hash) + + rootfs_path =3D os.path.join(self.workdir, 'rootfs.riscv32') + archive.lzma_uncompress(rootfs_path_xz, rootfs_path) + + self.vm.set_console() + kernel_command_line =3D 'root=3D/dev/vda ro console=3DttyS0' + self.vm.add_args('-kernel', kernel_path, + '-append', kernel_command_line, + '-drive', f'file=3D{rootfs_path},format=3Draw,id= =3Dhd0', + '-device', 'virtio-blk-device,drive=3Dhd0',) + self.vm.launch() + + console_pattern =3D 'Welcome to Buildroot' + self.wait_for_console_pattern(console_pattern) + exec_command(self, 'root') + time.sleep(0.1) + exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo', 'rv32= i') --=20 2.43.0