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Iglesias" , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v48 10/12] hw/sd/sdcard: Implement eMMC 'boot-mode' Date: Wed, 10 Jul 2024 16:14:06 +0200 Message-ID: <20240710141408.69275-11-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240710141408.69275-1-philmd@linaro.org> References: <20240710141408.69275-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::234; envelope-from=philmd@linaro.org; helo=mail-lj1-x234.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1720621066519116300 Spec v4.3 chapter 7.2.2 "Boot operation": If the CMD line is held LOW for 74 clock cycles and more after power-up before the first command is issued, the slave recognizes that boot mode is being initiated and starts preparing boot data internally. Track uptime since last reset, add the sd_uptime_ns() helper. When the first command is received, check at least 74 clocks are elapsed (during the identification phase, at a 10kHz rate) then enable BOOT_MODE in the Ext_CSD register. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/sd/sd.c | 38 ++++++++++++++++++++++++++++++++++++++ hw/sd/trace-events | 1 + 2 files changed, 39 insertions(+) diff --git a/hw/sd/sd.c b/hw/sd/sd.c index 57a9eb91d0..c2ea942389 100644 --- a/hw/sd/sd.c +++ b/hw/sd/sd.c @@ -163,6 +163,8 @@ struct SDState { */ bool expecting_acmd; uint32_t blk_written; + int64_t reset_time_ns; + uint32_t cmd_count; =20 uint64_t data_start; uint32_t data_offset; @@ -352,6 +354,11 @@ static uint8_t sd_crc7(const void *message, size_t wid= th) return shift_reg; } =20 +static int64_t sd_uptime_ns(SDState *sd) +{ + return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - sd->reset_time_ns; +} + /* Operation Conditions register */ =20 #define OCR_POWER_DELAY_NS 500000 /* 0.5ms */ @@ -479,6 +486,10 @@ static void emmc_set_cid(SDState *sd) #define CMULT_SHIFT 9 /* 512 times HWBLOCK_SIZE */ #define WPGROUP_SIZE (1 << (HWBLOCK_SHIFT + SECTOR_SHIFT + WPGROUP_SHIF= T)) =20 +#define OD_FREQ_MIN_HZ 10000 +#define OD_FREQ_MAX_HZ 400000 +#define BOOT_MODE_DELAY_CYCLES_MIN 74 + static const uint8_t sd_csd_rw_mask[16] =3D { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xfe, @@ -797,6 +808,8 @@ static void sd_reset(DeviceState *dev) =20 sect =3D sd_addr_to_wpnum(size) + 1; =20 + sd->reset_time_ns =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + sd->cmd_count =3D 0; sd->state =3D sd_idle_state; =20 /* card registers */ @@ -905,6 +918,18 @@ static const VMStateDescription emmc_extcsd_vmstate = =3D { }, }; =20 +static const VMStateDescription sdmmc_uptime_cmdcnt_vmstate =3D { + .name =3D "sd-card/uptime-command_count-state", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D vmstate_needed_for_emmc, + .fields =3D (const VMStateField[]) { + VMSTATE_INT64(reset_time_ns, SDState), + VMSTATE_UINT32(cmd_count, SDState), + VMSTATE_END_OF_LIST() + }, +}; + static int sd_vmstate_pre_load(void *opaque) { SDState *sd =3D opaque; @@ -953,6 +978,7 @@ static const VMStateDescription sd_vmstate =3D { .subsections =3D (const VMStateDescription * const []) { &sd_ocr_vmstate, &emmc_extcsd_vmstate, + &sdmmc_uptime_cmdcnt_vmstate, NULL }, }; @@ -1925,6 +1951,16 @@ static sd_rsp_type_t sd_cmd_SEND_OP_COND(SDState *sd= , SDRequest req) sd->state =3D sd_ready_state; } =20 + if (sd_is_emmc(sd) && sd->cmd_count =3D=3D 1) { + int64_t clk_cycles =3D sd_uptime_ns(sd) / OD_FREQ_MIN_HZ; + + trace_sdcard_ext_csd_bootmode(sd_uptime_ns(sd), clk_cycles, + clk_cycles > BOOT_MODE_DELAY_CYCLES_= MIN); + if (clk_cycles > BOOT_MODE_DELAY_CYCLES_MIN) { + sd->ext_csd[EXT_CSD_PART_CONFIG] |=3D (1 << 3); + } + } + return sd_r3; } =20 @@ -2107,6 +2143,8 @@ int sd_do_command(SDState *sd, SDRequest *req, return 0; } =20 + ++sd->cmd_count; + if (sd->state =3D=3D sd_inactive_state) { rtype =3D sd_illegal; goto send_response; diff --git a/hw/sd/trace-events b/hw/sd/trace-events index 5dfe6be7b7..7d0de368aa 100644 --- a/hw/sd/trace-events +++ b/hw/sd/trace-events @@ -57,6 +57,7 @@ sdcard_write_block(uint64_t addr, uint32_t len) "addr 0x%= " PRIx64 " size 0x%x" sdcard_write_data(const char *proto, const char *cmd_desc, uint8_t cmd, ui= nt32_t offset, uint8_t value) "%s %20s/ CMD%02d ofs %"PRIu32" value 0x%02x" sdcard_read_data(const char *proto, const char *cmd_desc, uint8_t cmd, uin= t32_t offset, uint64_t size, uint32_t blklen) "%s %20s/ CMD%02d ofs %"PRIu3= 2" size %"PRIu64" blklen %" PRIu32 sdcard_set_voltage(uint16_t millivolts) "%u mV" +sdcard_ext_csd_bootmode(int64_t uptime_ns, int64_t clk_cycles, unsigned en= abled) "%"PRId64" ns, %"PRId64" cycles, boot mode: %u" =20 # pxa2xx_mmci.c pxa2xx_mmci_read(uint8_t size, uint32_t addr, uint32_t value) "size %d add= r 0x%02x value 0x%08x" --=20 2.41.0