From nobody Sun Dec 29 00:15:39 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1721128669; cv=none; d=zohomail.com; s=zohoarc; b=c3XrXHnFHM8HEn2uPiWE/SRaxAoAGGpZf6vTW5+Zk4I1VgMpaUEkgKrjgsJhW1SPPHC2KFvUuXMKzbi4WZRnQuieIk89nyt5dIYqx/UYCsO+fDSD6+s0doNqQXKopZgc0IHKUTiiKzS4h+Kk/1Q4roqUBIDDwj8KmWhyfqgdoLc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1721128669; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=8oRR5Hlz48hwxOBsEZW6/9W3S3Cuh4qmeaeNYBLsFR4=; b=Pr7m0/XEf5BuqrQRH6ErT2zChvo/fOHyHRpqlPUKbDX1huYggVrHAaoFHwHIiM5Hn3lp8ewQDryOmD1z7yYCC/XpsgQW7xrKqSt4HI+vA83YhpZd425bONZP0mvBfAcleQ0Rm/B7EHd+4LRUmLrq3R0bKBcJD0QNAEuULTa7RN4= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1721128669861343.9396323101232; Tue, 16 Jul 2024 04:17:49 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sTgBT-0004gc-MM; Tue, 16 Jul 2024 07:17:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sTgBE-0004FJ-36; Tue, 16 Jul 2024 07:17:16 -0400 Received: from frasgout.his.huawei.com ([185.176.79.56]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sTgBC-0001nd-3Q; Tue, 16 Jul 2024 07:17:11 -0400 Received: from mail.maildlp.com (unknown [172.18.186.31]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4WNc0v13cSz6K99D; Tue, 16 Jul 2024 19:14:55 +0800 (CST) Received: from lhrpeml500001.china.huawei.com (unknown [7.191.163.213]) by mail.maildlp.com (Postfix) with ESMTPS id CFB3B1400C8; Tue, 16 Jul 2024 19:17:07 +0800 (CST) Received: from 00293818-MRGF.huawei.com (10.126.170.92) by lhrpeml500001.china.huawei.com (7.191.163.213) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Tue, 16 Jul 2024 12:16:49 +0100 To: , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Jonathan Cameron , Shaoqin Huang , Zhao Liu Subject: [PATCH V16 5/7] hw/acpi: Update CPUs AML with cpu-(ctrl)dev change Date: Tue, 16 Jul 2024 12:15:00 +0100 Message-ID: <20240716111502.202344-6-salil.mehta@huawei.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240716111502.202344-1-salil.mehta@huawei.com> References: <20240716111502.202344-1-salil.mehta@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.170.92] X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To lhrpeml500001.china.huawei.com (7.191.163.213) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=salil.mehta@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Salil Mehta From: Salil Mehta via Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZM-MESSAGEID: 1721128672044116300 Content-Type: text/plain; charset="utf-8" CPUs Control device(\\_SB.PCI0) register interface for the x86 arch is IO p= ort based and existing CPUs AML code assumes _CRS objects would evaluate to a s= ystem resource which describes IO Port address. But on ARM arch CPUs control device(\\_SB.PRES) register interface is memory-mapped hence _CRS object sh= ould evaluate to system resource which describes memory-mapped base address. Upd= ate build CPUs AML function to accept both IO/MEMORY region spaces and accordin= gly update the _CRS object. Co-developed-by: Keqian Zhu Signed-off-by: Keqian Zhu Signed-off-by: Salil Mehta Reviewed-by: Gavin Shan Tested-by: Vishnu Pajjuri Reviewed-by: Jonathan Cameron Tested-by: Xianglai Li Tested-by: Miguel Luis Reviewed-by: Shaoqin Huang Tested-by: Zhao Liu Reviewed-by: Igor Mammedov --- hw/acpi/cpu.c | 17 +++++++++++++---- hw/i386/acpi-build.c | 3 ++- include/hw/acpi/cpu.h | 5 +++-- 3 files changed, 18 insertions(+), 7 deletions(-) diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c index cf5e9183e4..5cb60ca8bc 100644 --- a/hw/acpi/cpu.c +++ b/hw/acpi/cpu.c @@ -338,9 +338,10 @@ const VMStateDescription vmstate_cpu_hotplug =3D { #define CPU_FW_EJECT_EVENT "CEJF" =20 void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures = opts, - build_madt_cpu_fn build_madt_cpu, hwaddr io_base, + build_madt_cpu_fn build_madt_cpu, hwaddr base_addr, const char *res_root, - const char *event_handler_method) + const char *event_handler_method, + AmlRegionSpace rs) { Aml *ifctx; Aml *field; @@ -364,14 +365,22 @@ void build_cpus_aml(Aml *table, MachineState *machine= , CPUHotplugFeatures opts, aml_name_decl("_UID", aml_string("CPU Hotplug resources"))); aml_append(cpu_ctrl_dev, aml_mutex(CPU_LOCK, 0)); =20 + assert((rs =3D=3D AML_SYSTEM_IO) || (rs =3D=3D AML_SYSTEM_MEMORY)); + crs =3D aml_resource_template(); - aml_append(crs, aml_io(AML_DECODE16, io_base, io_base, 1, + if (rs =3D=3D AML_SYSTEM_IO) { + aml_append(crs, aml_io(AML_DECODE16, base_addr, base_addr, 1, ACPI_CPU_HOTPLUG_REG_LEN)); + } else if (rs =3D=3D AML_SYSTEM_MEMORY) { + aml_append(crs, aml_memory32_fixed(base_addr, + ACPI_CPU_HOTPLUG_REG_LEN, AML_READ_WRITE)); + } + aml_append(cpu_ctrl_dev, aml_name_decl("_CRS", crs)); =20 /* declare CPU hotplug MMIO region with related access fields */ aml_append(cpu_ctrl_dev, - aml_operation_region("PRST", AML_SYSTEM_IO, aml_int(io_base), + aml_operation_region("PRST", rs, aml_int(base_addr), ACPI_CPU_HOTPLUG_REG_LEN)); =20 field =3D aml_field("PRST", AML_BYTE_ACC, AML_NOLOCK, diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index f4e366f64f..5d4bd2b710 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -1536,7 +1536,8 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, .fw_unplugs_cpu =3D pm->smi_on_cpu_unplug, }; build_cpus_aml(dsdt, machine, opts, pc_madt_cpu_entry, - pm->cpu_hp_io_base, "\\_SB.PCI0", "\\_GPE._E02"); + pm->cpu_hp_io_base, "\\_SB.PCI0", "\\_GPE._E02", + AML_SYSTEM_IO); } =20 if (pcms->memhp_io_base && nr_mem) { diff --git a/include/hw/acpi/cpu.h b/include/hw/acpi/cpu.h index df87b15997..32654dc274 100644 --- a/include/hw/acpi/cpu.h +++ b/include/hw/acpi/cpu.h @@ -63,9 +63,10 @@ typedef void (*build_madt_cpu_fn)(int uid, const CPUArch= IdList *apic_ids, GArray *entry, bool force_enabled); =20 void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures = opts, - build_madt_cpu_fn build_madt_cpu, hwaddr io_base, + build_madt_cpu_fn build_madt_cpu, hwaddr base_addr, const char *res_root, - const char *event_handler_method); + const char *event_handler_method, + AmlRegionSpace rs); =20 void acpi_cpu_ospm_status(CPUHotplugState *cpu_st, ACPIOSTInfoList ***list= ); =20 --=20 2.34.1