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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1721197864; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=bRmL0OYaoeGHe5hCmTex3w/LL9vR1msP0rIYrY1NERE=; b=a+TfStcjmugY754djoifR1gF494i0IT9PJlTQGZiGqfwT7mXaf+fdOlyvptymqdZMFzkF7 QyhSPngdpeGWQDhM5OtaUDxhM0PoGBJBMKOU+Ll2wxVDxVDRAbDj5sDLbz4olwlGD8zXxY Iw4jXZIF4hRirHPtFTNvClIzOw6vQ1E= X-MC-Unique: kTTV2iIjNmihFa32piaE9A-1 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Andrew Jeffery , Joel Stanley , Steven Lee , Troy Lee , Jamin Lin , Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v2 4/8] aspeed: Introduce a AspeedSoCClass 'boot_from_emmc' handler Date: Wed, 17 Jul 2024 08:30:18 +0200 Message-ID: <20240717063022.549849-5-clg@redhat.com> In-Reply-To: <20240717063022.549849-1-clg@redhat.com> References: <20240717063022.549849-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1721197915424116300 From: C=C3=A9dric Le Goater Report support on the AST2600 SoC if the boot-from-eMMC HW strapping bit is set at the board level. AST2700 also has support but it is not yet ready in QEMU and others SoCs do not have support, so return false always for these. Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: Andrew Jeffery Tested-by: Andrew Jeffery --- include/hw/arm/aspeed_soc.h | 1 + hw/arm/aspeed_ast2600.c | 8 ++++++++ hw/arm/aspeed_soc_common.c | 7 +++++++ 3 files changed, 16 insertions(+) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 849ba37f9524..624d489e0d63 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -164,6 +164,7 @@ struct AspeedSoCClass { const hwaddr *memmap; uint32_t num_cpus; qemu_irq (*get_irq)(AspeedSoCState *s, int dev); + bool (*boot_from_emmc)(AspeedSoCState *s); }; =20 const char *aspeed_soc_cpu_type(AspeedSoCClass *sc); diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index 31713de74a5f..be3eb70cdd77 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -646,6 +646,13 @@ static void aspeed_soc_ast2600_realize(DeviceState *de= v, Error **errp) } } =20 +static bool aspeed_soc_ast2600_boot_from_emmc(AspeedSoCState *s) +{ + uint32_t hw_strap1 =3D object_property_get_uint(OBJECT(&s->scu), + "hw-strap1", &error_abor= t); + return !!(hw_strap1 & SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC); +} + static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) { static const char * const valid_cpu_types[] =3D { @@ -673,6 +680,7 @@ static void aspeed_soc_ast2600_class_init(ObjectClass *= oc, void *data) sc->memmap =3D aspeed_soc_ast2600_memmap; sc->num_cpus =3D 2; sc->get_irq =3D aspeed_soc_ast2600_get_irq; + sc->boot_from_emmc =3D aspeed_soc_ast2600_boot_from_emmc; } =20 static const TypeInfo aspeed_soc_ast2600_types[] =3D { diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c index 1e8f2558fdc2..05551461aea0 100644 --- a/hw/arm/aspeed_soc_common.c +++ b/hw/arm/aspeed_soc_common.c @@ -134,6 +134,11 @@ static void aspeed_soc_realize(DeviceState *dev, Error= **errp) } } =20 +static bool aspeed_soc_boot_from_emmc(AspeedSoCState *s) +{ + return false; +} + static Property aspeed_soc_properties[] =3D { DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION, MemoryRegion *), @@ -145,9 +150,11 @@ static Property aspeed_soc_properties[] =3D { static void aspeed_soc_class_init(ObjectClass *oc, void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); + AspeedSoCClass *sc =3D ASPEED_SOC_CLASS(oc); =20 dc->realize =3D aspeed_soc_realize; device_class_set_props(dc, aspeed_soc_properties); + sc->boot_from_emmc =3D aspeed_soc_boot_from_emmc; } =20 static const TypeInfo aspeed_soc_types[] =3D { --=20 2.45.2