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i=@fujitsu.com; q=dns/txt; s=fj2; t=1721206596; x=1752742596; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=sVI0RniNYi0W5BbxKf/SmIGPggwqI+jvDgAGkKB2HVk=; b=Y57iWAFr9baElUGdBkwv4aOnjrsA/l9SIrCh4TiMrK7PlUJoyiW0Ccy4 7TfUGuFlYF/hJaG1bGgQMvLq4z5JPe6oYB/J/gXm8bULA17H7MlNGftQ7 LgMJa2KJ2jItZfFU+JHmR6PUvlHCx5jcxa2GTU62cyJxzPuSZou2jnRCp MhgN+wc6vXA03v8SJyPXzuuzKYCxlPEKWJcK7dRAvT9gaC3iLSX3DHTBF qGP/dflP07Hs3QgqwNMeDc2Z0ip2tSFjVi/Zz6ikvEwwKVhXO12JGB5jI kz6iJqNQo1e6LH1GPjkV7I2D/ev47nlT2ztIDWVPLrKigz6j4S2cAQnyM A==; X-IronPort-AV: E=McAfee;i="6700,10204,11135"; a="167551159" X-IronPort-AV: E=Sophos;i="6.09,214,1716217200"; d="scan'208";a="167551159" To: mst@redhat.com, marcel.apfelbaum@gmail.com Cc: qemu-devel@nongnu.org, jonathan.cameron@huawei.com, Yao Xingtao Subject: [PATCH v2] pci-bridge: avoid linking a single downstream port more than once Date: Wed, 17 Jul 2024 04:56:21 -0400 Message-Id: <20240717085621.55315-1-yaoxt.fnst@fujitsu.com> X-Mailer: git-send-email 2.37.3 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-TM-AS-Product-Ver: IMSS-9.1.0.1417-9.0.0.1002-28534.005 X-TM-AS-User-Approved-Sender: Yes X-TMASE-Version: IMSS-9.1.0.1417-9.0.1002-28534.005 X-TMASE-Result: 10--6.176500-10.000000 X-TMASE-MatchedRID: Yt5+J3IIlN56bMYbioM9qazGfgakLdjaBGvINcfHqhcOabErRKSRvego SvaKsl/kIvrftAIhWmLy9zcRSkKatWA1R1xiceE7s0T0PE+KHuVYjHef2XEWkQZZ8N3RvTMxo8W MkQWv6iXBcIE78YqRWvcUt5lc1lLgOMB0shqXhHrEADU5fwfpWn1Whz8oylpkqoRmqV8XOn7SyQ /OlZbotvkcX3eSdgyP X-TMASE-SNAP-Result: 1.821001.0001-0-1-22:0,33:0,34:0-0 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=207.54.90.49; envelope-from=yaoxt.fnst@fujitsu.com; helo=esa3.hc1455-7.c3s2.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Yao Xingtao From: Yao Xingtao via Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1721206621780116300 Content-Type: text/plain; charset="utf-8" Since the downstream port is not checked, two slots can be linked to a single port. However, this can prevent the driver from detecting the device properly. It is necessary to ensure that a downstream port is not linked more than once. Links: https://lore.kernel.org/qemu-devel/OSZPR01MB6453BC61D2FF4035F18084EF= 8DDC2@OSZPR01MB6453.jpnprd01.prod.outlook.com Signed-off-by: Yao Xingtao --- V1[1] -> V2: - Move downstream port check forward [1] https://lore.kernel.org/qemu-devel/20240704033834.3362-1-yaoxt.fnst@fuj= itsu.com --- hw/pci-bridge/cxl_downstream.c | 5 +++++ hw/pci-bridge/pcie_root_port.c | 5 +++++ hw/pci-bridge/xio3130_downstream.c | 5 +++++ 3 files changed, 15 insertions(+) diff --git a/hw/pci-bridge/cxl_downstream.c b/hw/pci-bridge/cxl_downstream.c index 742da07a015a..af81ddfeec13 100644 --- a/hw/pci-bridge/cxl_downstream.c +++ b/hw/pci-bridge/cxl_downstream.c @@ -142,6 +142,11 @@ static void cxl_dsp_realize(PCIDevice *d, Error **errp) MemoryRegion *component_bar =3D &cregs->component_registers; int rc; =20 + if (pcie_find_port_by_pn(pci_get_bus(d), p->port) !=3D NULL) { + error_setg(errp, "Can't link port, error %d", -EBUSY); + return; + } + pci_bridge_initfn(d, TYPE_PCIE_BUS); pcie_port_init_reg(d); =20 diff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c index 09a34786bc62..a540204bda27 100644 --- a/hw/pci-bridge/pcie_root_port.c +++ b/hw/pci-bridge/pcie_root_port.c @@ -67,6 +67,11 @@ static void rp_realize(PCIDevice *d, Error **errp) PCIERootPortClass *rpc =3D PCIE_ROOT_PORT_GET_CLASS(d); int rc; =20 + if (pcie_find_port_by_pn(pci_get_bus(d), p->port) !=3D NULL) { + error_setg(errp, "Can't link port, error %d", -EBUSY); + return; + } + pci_config_set_interrupt_pin(d->config, 1); if (d->cap_present & QEMU_PCIE_CAP_CXL) { pci_bridge_initfn(d, TYPE_CXL_BUS); diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_dow= nstream.c index 907d5105b019..63f6baa615fd 100644 --- a/hw/pci-bridge/xio3130_downstream.c +++ b/hw/pci-bridge/xio3130_downstream.c @@ -69,6 +69,11 @@ static void xio3130_downstream_realize(PCIDevice *d, Err= or **errp) PCIESlot *s =3D PCIE_SLOT(d); int rc; =20 + if (pcie_find_port_by_pn(pci_get_bus(d), p->port) !=3D NULL) { + error_setg(errp, "Can't link port, error %d", -EBUSY); + return; + } + pci_bridge_initfn(d, TYPE_PCIE_BUS); pcie_port_init_reg(d); =20 --=20 2.37.3