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[2403:580b:97e8:0:82ce:f179:8a79:69f4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fc0bba949bsm81999385ad.69.2024.07.17.19.11.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Jul 2024 19:11:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1721268696; x=1721873496; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=E8cWbKkT7M84MGGAu2FLVm64KRcLw5vpyDYslYBj4tE=; b=NnCYTEu4pSC9X2bicFdYNo6ShW8jpKuDbGhTe6wj89L2Q05M7m5W/z4F8Lm/QS0LUU o07viCfjeyJzo5e9Ak1wLGWhzkB+8Zah0VwzELSMrSMhiJlhVSW17z6HSNgulhPA2nEy nRqkbrnlnQITcHWAOSZ61wyMY75yXsv888rD3mnc8U+hER4p7hujhxjQGLVX7bVnhQAj Pdhn7Ml+CaTgIKSGhxrzz+kxMyzF88RBdoIYDDaGY78FSThWCTclu5siCt2n8Q33A1Te Tryj8MPZvYOgL3Zr3bqg/5wVs+b/Zocf+SujfuKFZxADjbsgubqYw2ZvVq7e6jtHSisJ 8xYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721268696; x=1721873496; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=E8cWbKkT7M84MGGAu2FLVm64KRcLw5vpyDYslYBj4tE=; b=djRI3MkmOGLuLi2OuX1y9hMJAB9vz1pr8IqoCoWhteQLxwOXGOY3VQCnIxeCltoAvR cssAUF1CnRFb/E8rUzEFCM7uBd4W8UtMzJtLuUKTikJ/lpbPYaCpgLeV3O/ntpd5G2jk jUwu+fPDq6hpbcrbE9FS+zt3iCfi30GhK1RX73oORpDXdqFys7J3yxbl9+eETVfuuDuv bRQBi60GhSfmtSkRD0Ftpl/XqLf8KP7N87+ed3hgfPldYcUu/q4FpeRmseYHxtinDQqS K968zUXnkaDiKuI54pbx8alsR6xEIzgIr1wgMnCrxqD5eC4BZ3hdOG7G/vzL/f6RaGsE gMxw== X-Gm-Message-State: AOJu0YzN+3pK1b5ZGKUdphtNpRcYc3nAECaCohaNo+AZ5WqEthomd4Qm cQkPDf1Xl+RundTQYBUjLHEBy5YHy5AYMtj33hqfr+wpBQOhlzEDqSn6NUU8 X-Google-Smtp-Source: AGHT+IGmSpFJZhzDezMU4xo0dalYdR5wapFOpxhZFivPHcluNSXFNOyCNdNvXtuPt893/eHHULcO2A== X-Received: by 2002:a17:902:ea04:b0:1fb:9a83:4496 with SMTP id d9443c01a7336-1fc4e11f2e5mr31108875ad.2.1721268695773; Wed, 17 Jul 2024 19:11:35 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Rajnesh Kanwal , Daniel Henrique Barboza , Alistair Francis Subject: [PULL 24/30] target/riscv: Start counters from both mhpmcounter and mcountinhibit Date: Thu, 18 Jul 2024 12:10:06 +1000 Message-ID: <20240718021012.2057986-25-alistair.francis@wdc.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240718021012.2057986-1-alistair.francis@wdc.com> References: <20240718021012.2057986-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62b.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1721268896406116300 Content-Type: text/plain; charset="utf-8" From: Rajnesh Kanwal Currently we start timer counter from write_mhpmcounter path only without checking for mcountinhibit bit. This changes adds mcountinhibit check and also programs the counter from write_mcountinhibit as well. When a counter is stopped using mcountinhibit we simply update the value of the counter based on current host ticks and save it for future reads. We don't need to disable running timer as pmu_timer_trigger_irq will discard the interrupt if the counter has been inhibited. Signed-off-by: Rajnesh Kanwal Reviewed-by: Daniel Henrique Barboza Message-ID: <20240711-smcntrpmf_v7-v8-10-b7c38ae7b263@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/csr.c | 75 ++++++++++++++++++++++++++++++++-------------- target/riscv/pmu.c | 3 +- 2 files changed, 54 insertions(+), 24 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d6c5b73afd..bb6ac33ac2 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1077,8 +1077,9 @@ static RISCVException write_mhpmcounter(CPURISCVState= *env, int csrno, uint64_t mhpmctr_val =3D val; =20 counter->mhpmcounter_val =3D val; - if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || - riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { + if (!get_field(env->mcountinhibit, BIT(ctr_idx)) && + (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || + riscv_pmu_ctr_monitor_instructions(env, ctr_idx))) { counter->mhpmcounter_prev =3D riscv_pmu_ctr_get_fixed_counters_val= (env, ctr_idx, f= alse); if (ctr_idx > 2) { @@ -1106,8 +1107,9 @@ static RISCVException write_mhpmcounterh(CPURISCVStat= e *env, int csrno, =20 counter->mhpmcounterh_val =3D val; mhpmctr_val =3D mhpmctr_val | (mhpmctrh_val << 32); - if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || - riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { + if (!get_field(env->mcountinhibit, BIT(ctr_idx)) && + (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || + riscv_pmu_ctr_monitor_instructions(env, ctr_idx))) { counter->mhpmcounterh_prev =3D riscv_pmu_ctr_get_fixed_counters_va= l(env, ctr_idx, = true); if (ctr_idx > 2) { @@ -2170,31 +2172,60 @@ static RISCVException write_mcountinhibit(CPURISCVS= tate *env, int csrno, int cidx; PMUCTRState *counter; RISCVCPU *cpu =3D env_archcpu(env); + uint32_t present_ctrs =3D cpu->pmu_avail_ctrs | COUNTEREN_CY | COUNTER= EN_IR; + target_ulong updated_ctrs =3D (env->mcountinhibit ^ val) & present_ctr= s; + uint64_t mhpmctr_val, prev_count, curr_count; =20 /* WARL register - disable unavailable counters; TM bit is always 0 */ - env->mcountinhibit =3D - val & (cpu->pmu_avail_ctrs | COUNTEREN_CY | COUNTEREN_IR); + env->mcountinhibit =3D val & present_ctrs; =20 /* Check if any other counter is also monitoring cycles/instructions */ for (cidx =3D 0; cidx < RV_MAX_MHPMCOUNTERS; cidx++) { - counter =3D &env->pmu_ctrs[cidx]; - if (get_field(env->mcountinhibit, BIT(cidx)) && (val & BIT(cidx)))= { - /* - * Update the counter value for cycle/instret as we can't stop= the - * host ticks. But we should show the current value at this mo= ment. - */ - if (riscv_pmu_ctr_monitor_cycles(env, cidx) || - riscv_pmu_ctr_monitor_instructions(env, cidx)) { - counter->mhpmcounter_val =3D - riscv_pmu_ctr_get_fixed_counters_val(env, cidx, false)= - - counter->mhpmcounter_prev + - counter->mhpmcounter_val; + if (!(updated_ctrs & BIT(cidx)) || + (!riscv_pmu_ctr_monitor_cycles(env, cidx) && + !riscv_pmu_ctr_monitor_instructions(env, cidx))) { + continue; + } + + counter =3D &env->pmu_ctrs[cidx]; + + if (!get_field(env->mcountinhibit, BIT(cidx))) { + counter->mhpmcounter_prev =3D + riscv_pmu_ctr_get_fixed_counters_val(env, cidx, false); + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { + counter->mhpmcounterh_prev =3D + riscv_pmu_ctr_get_fixed_counters_val(env, cidx, true); + } + + if (cidx > 2) { + mhpmctr_val =3D counter->mhpmcounter_val; if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { - counter->mhpmcounterh_val =3D - riscv_pmu_ctr_get_fixed_counters_val(env, cidx, tr= ue) - - counter->mhpmcounterh_prev= + - counter->mhpmcounterh_val; + mhpmctr_val =3D mhpmctr_val | + ((uint64_t)counter->mhpmcounterh_val << 32); } + riscv_pmu_setup_timer(env, mhpmctr_val, cidx); + } + } else { + curr_count =3D riscv_pmu_ctr_get_fixed_counters_val(env, cidx,= false); + + mhpmctr_val =3D counter->mhpmcounter_val; + prev_count =3D counter->mhpmcounter_prev; + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { + uint64_t tmp =3D + riscv_pmu_ctr_get_fixed_counters_val(env, cidx, true); + + curr_count =3D curr_count | (tmp << 32); + mhpmctr_val =3D mhpmctr_val | + ((uint64_t)counter->mhpmcounterh_val << 32); + prev_count =3D prev_count | + ((uint64_t)counter->mhpmcounterh_prev << 32); + } + + /* Adjust the counter for later reads. */ + mhpmctr_val =3D curr_count - prev_count + mhpmctr_val; + counter->mhpmcounter_val =3D mhpmctr_val; + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { + counter->mhpmcounterh_val =3D mhpmctr_val >> 32; } } } diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index ac648cff8d..63420d9f36 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -285,8 +285,7 @@ int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_ev= ent_idx event_idx) } =20 ctr_idx =3D GPOINTER_TO_UINT(value); - if (!riscv_pmu_counter_enabled(cpu, ctr_idx) || - get_field(env->mcountinhibit, BIT(ctr_idx))) { + if (!riscv_pmu_counter_enabled(cpu, ctr_idx)) { return -1; } =20 --=20 2.45.2