From nobody Thu Sep 19 00:15:30 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1721285491; cv=none; d=zohomail.com; s=zohoarc; b=BrP+M5pBebtAn9V17Q7rofRt0hzua3ovQ6JFkl+r5cNE1/mEN59cSM8TK/pN5xbpSzikgai55zYPe0RxtkmDqV4rbLbaw7YjeJPkmST7W3q60xYqrAZ82mQ/dKiQfoMnCB68QZxn3xGlE6HM1RjVRYZwf6XRaV434m1V/5NNeCg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1721285491; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=Fn27Okcfa+2nqZsUvxMQA7sfPh4A42Y8CLhemfiOMF8=; b=RC4Sa9jyHrtqWAOWdNHgmK+x7hgye6WPHFApVra5oOjMCFDr5mDORObrZUfGklO7bqlhMrMVNtqNhpa5xGSjiNofkRJRuv1CdqnnytlKhJITkgB0hZDSkSUj9xy6Jqkuq70YtWdhWcoYYH+acK53tag35eS2wLQode0SS4Y4Hj8= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1721285491885759.5316712494447; Wed, 17 Jul 2024 23:51:31 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sUKyB-0005IQ-0m; Thu, 18 Jul 2024 02:50:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sUKy9-0005Cr-KI; Thu, 18 Jul 2024 02:50:25 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sUKy8-0004L5-3a; Thu, 18 Jul 2024 02:50:25 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Thu, 18 Jul 2024 14:50:15 +0800 Received: from localhost.localdomain (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Thu, 18 Jul 2024 14:50:15 +0800 To: Alistair Francis , Peter Maydell , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:STM32F205" , "open list:All patches CC here" CC: , , Subject: [PATCH v1 03/15] hw/i2c/aspeed: support to set the different memory size Date: Thu, 18 Jul 2024 14:49:13 +0800 Message-ID: <20240718064925.1846074-4-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240718064925.1846074-1-jamin_lin@aspeedtech.com> References: <20240718064925.1846074-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZM-MESSAGEID: 1721285492451116300 Content-Type: text/plain; charset="utf-8" According to the datasheet of ASPEED SOCs, an I2C controller owns 8KB of register space for AST2700, owns 4KB of register space for AST2600, AST2500 and AST2400, and owns 64KB of register space for AST1030. It set the memory region size 4KB by default and it does not compatible register space for AST2700. Introduce a new class attribute to set the I2C controller memory size for different ASPEED SOCs. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- hw/i2c/aspeed_i2c.c | 6 +++++- include/hw/i2c/aspeed_i2c.h | 2 +- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c index b43afd250d..7d5a53c4c0 100644 --- a/hw/i2c/aspeed_i2c.c +++ b/hw/i2c/aspeed_i2c.c @@ -1014,7 +1014,7 @@ static void aspeed_i2c_realize(DeviceState *dev, Erro= r **errp) =20 sysbus_init_irq(sbd, &s->irq); memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_i2c_ctrl_ops, s, - "aspeed.i2c", 0x1000); + "aspeed.i2c", aic->mem_size); sysbus_init_mmio(sbd, &s->iomem); =20 for (i =3D 0; i < aic->num_busses; i++) { @@ -1286,6 +1286,7 @@ static void aspeed_2400_i2c_class_init(ObjectClass *k= lass, void *data) aic->pool_size =3D 0x800; aic->pool_base =3D 0x800; aic->bus_pool_base =3D aspeed_2400_i2c_bus_pool_base; + aic->mem_size =3D 0x1000; } =20 static const TypeInfo aspeed_2400_i2c_info =3D { @@ -1320,6 +1321,7 @@ static void aspeed_2500_i2c_class_init(ObjectClass *k= lass, void *data) aic->bus_pool_base =3D aspeed_2500_i2c_bus_pool_base; aic->check_sram =3D true; aic->has_dma =3D true; + aic->mem_size =3D 0x1000; } =20 static const TypeInfo aspeed_2500_i2c_info =3D { @@ -1353,6 +1355,7 @@ static void aspeed_2600_i2c_class_init(ObjectClass *k= lass, void *data) aic->pool_base =3D 0xC00; aic->bus_pool_base =3D aspeed_2600_i2c_bus_pool_base; aic->has_dma =3D true; + aic->mem_size =3D 0x1000; } =20 static const TypeInfo aspeed_2600_i2c_info =3D { @@ -1376,6 +1379,7 @@ static void aspeed_1030_i2c_class_init(ObjectClass *k= lass, void *data) aic->pool_base =3D 0xC00; aic->bus_pool_base =3D aspeed_2600_i2c_bus_pool_base; aic->has_dma =3D true; + aic->mem_size =3D 0x10000; } =20 static const TypeInfo aspeed_1030_i2c_info =3D { diff --git a/include/hw/i2c/aspeed_i2c.h b/include/hw/i2c/aspeed_i2c.h index a064479e59..065b636d29 100644 --- a/include/hw/i2c/aspeed_i2c.h +++ b/include/hw/i2c/aspeed_i2c.h @@ -283,7 +283,7 @@ struct AspeedI2CClass { uint8_t *(*bus_pool_base)(AspeedI2CBus *); bool check_sram; bool has_dma; - + uint64_t mem_size; }; =20 static inline bool aspeed_i2c_is_new_mode(AspeedI2CState *s) --=20 2.34.1