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a="29996408" X-IronPort-AV: E=Sophos;i="6.09,217,1716274800"; d="scan'208";a="29996408" X-CSE-ConnectionGUID: +JAKjvN4SJW1kbaGJ5zlyA== X-CSE-MsgGUID: wXDASGxoTSq5U7qpeTKrVw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,217,1716274800"; d="scan'208";a="81717547" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, peterx@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum Subject: [PATCH v1 15/17] intel_iommu: Set default aw_bits to 48 in scalable modren mode Date: Thu, 18 Jul 2024 16:16:34 +0800 Message-Id: <20240718081636.879544-16-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240718081636.879544-1-zhenzhong.duan@intel.com> References: <20240718081636.879544-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.13; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1721290899161116300 Content-Type: text/plain; charset="utf-8" According to VTD spec, stage-1 page table could support 4-level and 5-level paging. However, 5-level paging translation emulation is unsupported yet. That means the only supported value for aw_bits is 48. So default aw_bits to 48 in scalable modern mode. In other cases, it is still default to 39 for compatibility. Add a check to ensure user specified value is 48 in modern mode for now. Signed-off-by: Zhenzhong Duan Reviewed-by: Cl=C3=A9ment Mathieu--Drif --- include/hw/i386/intel_iommu.h | 2 +- hw/i386/intel_iommu.c | 16 +++++++++++++++- 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index b843d069cc..48134bda11 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -45,7 +45,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(IntelIOMMUState, INTEL_IOMMU_D= EVICE) #define DMAR_REG_SIZE 0x230 #define VTD_HOST_AW_39BIT 39 #define VTD_HOST_AW_48BIT 48 -#define VTD_HOST_ADDRESS_WIDTH VTD_HOST_AW_39BIT +#define VTD_HOST_AW_AUTO 0xff #define VTD_HAW_MASK(aw) ((1ULL << (aw)) - 1) =20 #define DMAR_REPORT_F_INTR (1) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index c0116497b1..2804c3628a 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -3768,7 +3768,7 @@ static Property vtd_properties[] =3D { ON_OFF_AUTO_AUTO), DEFINE_PROP_BOOL("x-buggy-eim", IntelIOMMUState, buggy_eim, false), DEFINE_PROP_UINT8("aw-bits", IntelIOMMUState, aw_bits, - VTD_HOST_ADDRESS_WIDTH), + VTD_HOST_AW_AUTO), DEFINE_PROP_BOOL("caching-mode", IntelIOMMUState, caching_mode, FALSE), DEFINE_PROP_BOOL("x-scalable-mode", IntelIOMMUState, scalable_mode, FA= LSE), DEFINE_PROP_BOOL("snoop-control", IntelIOMMUState, snoop_control, fals= e), @@ -4686,6 +4686,14 @@ static bool vtd_decide_config(IntelIOMMUState *s, Er= ror **errp) } } =20 + if (s->aw_bits =3D=3D VTD_HOST_AW_AUTO) { + if (s->scalable_modern) { + s->aw_bits =3D VTD_HOST_AW_48BIT; + } else { + s->aw_bits =3D VTD_HOST_AW_39BIT; + } + } + if ((s->aw_bits !=3D VTD_HOST_AW_39BIT) && (s->aw_bits !=3D VTD_HOST_AW_48BIT) && !s->scalable_modern) { @@ -4694,6 +4702,12 @@ static bool vtd_decide_config(IntelIOMMUState *s, Er= ror **errp) return false; } =20 + if ((s->aw_bits !=3D VTD_HOST_AW_48BIT) && s->scalable_modern) { + error_setg(errp, "Supported values for aw-bits are: %d", + VTD_HOST_AW_48BIT); + return false; + } + if (s->scalable_mode && !s->dma_drain) { error_setg(errp, "Need to set dma_drain for scalable mode"); return false; --=20 2.34.1