From nobody Thu Sep 19 02:00:40 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1721292098; cv=none; d=zohomail.com; s=zohoarc; b=KMCnJrpdrOCaCXZi5hxpg4latsBYsADu5WygAQ8OtkTCQ/J3N81ZLAFcfg3mqQ+Gdgquzgfa4G4PTdwoszGHLfOGbR2Y65eyxZExmBsNBVE6Vo44yiN3m3qLiuoL2Hyq5yP45KFpIDJjYvAl+3WEVGWibk75k7llgf0T1W1RJ34= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1721292098; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=QAAADLqB/ywse+fbm4/hNi0SZ7JLjPzn4jkX3T2CABk=; b=dQ1b8grk5jqWpY1qF/SJp8HgyPXejcIp+fBGyWjHW+3YzdSNa5z3fyTuwh/KmRGMQyPQgcSNkGkGDJSGw6FNH9R87XX1TDQlcdBFJU4V4lljU/eyoMk0zNI/0r1wyo8kajAI71PhXiJnhVXfjjB+B0anOhJGTdn+Ch7mbhxxZrs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1721292098265370.84364505398; Thu, 18 Jul 2024 01:41:38 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sUMgy-0002b2-5C; Thu, 18 Jul 2024 04:40:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sUMgo-0001oE-Ia for qemu-devel@nongnu.org; Thu, 18 Jul 2024 04:40:39 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sUMgl-0005Kq-Ri for qemu-devel@nongnu.org; Thu, 18 Jul 2024 04:40:38 -0400 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-427cede1e86so539875e9.0 for ; Thu, 18 Jul 2024 01:40:34 -0700 (PDT) Received: from localhost.localdomain ([176.187.208.21]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-427d2b18420sm1394705e9.19.2024.07.18.01.40.30 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 18 Jul 2024 01:40:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1721292033; x=1721896833; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QAAADLqB/ywse+fbm4/hNi0SZ7JLjPzn4jkX3T2CABk=; b=MWtphYh2pGMrz0NlMS8Rsq51ITwD5jjEAftER/0wxIUbs22XixTN7FloSNKaAMw7hT L/4OUWsBsPp93fW8MRueGLZDcmvu3GwSaoUiJtrj3LTQYTK/veymm+0KMZOavbDEnpuN CbmQ+aOjBJk3Jvw3/8ePVdOl+Xo2RnFp7fMdUlmupL9GCe7E94xE84z6BvVoAXCDurzS CJbD8dUhAEr06bCJ9XI86AKOEg2yr1psQrKcCnaqHEx8adeaaJQ+Ba6z1kLAGAzwXU0L yaKmzgqZSbYn7nZOhzKyivppwakpoNRMJZ49KXH7t+f9x8O+BqROOutam7xqDfkXloqF XMYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721292033; x=1721896833; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QAAADLqB/ywse+fbm4/hNi0SZ7JLjPzn4jkX3T2CABk=; b=U7Py5T06lriWLDd6lH6MdGNC6uxrcoeuN1D+0nTRru2c+aox4VenuAcdRd06YYk+J6 PLnPU/mRfZ17g5GuiBJdEIeP9s1ePv+eCeXsPVb8mhPT3oj1wbfuTmGGJw3gxZcSStfk zHu0IxDiNdixvl6bQjpXEgxFbV9tAxXFbDIzX6H9eR3gDOQfxtcZRBo93VmFp+uSkFKM OvV4PvjlnEdhB3p77aprZTfScLg43YLdcLsd446Zw80NMKZRN35gf9XikX6LcSQ+ol47 BRSws/YsSqC8JgOQG09vE/Ga10jONlnOjrtumwovVNoqs5MUZnvMVlcgim0vn59uxBE/ kYdQ== X-Gm-Message-State: AOJu0YzaAYVtXngnwKkrxywo6nUqgabawPKnAI9p1A5uPWInJliqKd8j 0n2iRtF3QxY/KR/0rrlBm38wLnLr4vYA/ARvEUcdYetcPwjDo84FSO9Tmj37bd8H43TEuSb5Uxd lb3c= X-Google-Smtp-Source: AGHT+IHnd30ODg3Xo4FGMO8hg5Y7zY6CXHAtyIkJCcWIiu3bmB5yz2lBHJshqB0F7dC7rid6P1AQdw== X-Received: by 2002:a05:600c:474c:b0:426:5e91:3920 with SMTP id 5b1f17b1804b1-427c2cf2791mr34388825e9.29.1721292033015; Thu, 18 Jul 2024 01:40:33 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Bibo Mao , Jiaxun Yang Cc: Song Gao , Xianglai Li , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Xiaojuan Yang , Paolo Bonzini Subject: [PATCH v4 14/18] hw/intc/loongson_ipi: Move common code to loongson_ipi_common.c Date: Thu, 18 Jul 2024 10:38:38 +0200 Message-ID: <20240718083842.81199-15-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240718083842.81199-1-philmd@linaro.org> References: <20240718083842.81199-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1721292099374116300 From: Bibo Mao Move the common code from loongson_ipi.c to loongson_ipi_common.c, call parent_realize() instead of loongson_ipi_common_realize() in loongson_ipi_realize(). Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Bibo Mao Tested-by: Bibo Mao Reviewed-by: Richard Henderson --- hw/intc/loongson_ipi.c | 269 +-------------------------------- hw/intc/loongson_ipi_common.c | 272 ++++++++++++++++++++++++++++++++++ 2 files changed, 274 insertions(+), 267 deletions(-) diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index a2db8bb2e2..86badb2972 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -24,56 +24,6 @@ #endif #include "trace.h" =20 -MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, uint64_t *d= ata, - unsigned size, MemTxAttrs attrs) -{ - IPICore *s =3D opaque; - uint64_t ret =3D 0; - int index =3D 0; - - addr &=3D 0xff; - switch (addr) { - case CORE_STATUS_OFF: - ret =3D s->status; - break; - case CORE_EN_OFF: - ret =3D s->en; - break; - case CORE_SET_OFF: - ret =3D 0; - break; - case CORE_CLEAR_OFF: - ret =3D 0; - break; - case CORE_BUF_20 ... CORE_BUF_38 + 4: - index =3D (addr - CORE_BUF_20) >> 2; - ret =3D s->buf[index]; - break; - default: - qemu_log_mask(LOG_UNIMP, "invalid read: %x", (uint32_t)addr); - break; - } - - trace_loongson_ipi_read(size, (uint64_t)addr, ret); - *data =3D ret; - return MEMTX_OK; -} - -static MemTxResult loongson_ipi_iocsr_readl(void *opaque, hwaddr addr, - uint64_t *data, - unsigned size, MemTxAttrs attr= s) -{ - LoongsonIPICommonState *ipi =3D opaque; - IPICore *s; - - if (attrs.requester_id >=3D ipi->num_cpu) { - return MEMTX_DECODE_ERROR; - } - - s =3D &ipi->cpu[attrs.requester_id]; - return loongson_ipi_core_readl(s, addr, data, size, attrs); -} - #ifdef TARGET_LOONGARCH64 static AddressSpace *get_iocsr_as(CPUState *cpu) { @@ -92,148 +42,6 @@ static AddressSpace *get_iocsr_as(CPUState *cpu) } #endif =20 -static MemTxResult send_ipi_data(LoongsonIPICommonState *ipi, CPUState *cp= u, - uint64_t val, hwaddr addr, MemTxAttrs att= rs) -{ - LoongsonIPICommonClass *licc =3D LOONGSON_IPI_COMMON_GET_CLASS(ipi); - int i, mask =3D 0, data =3D 0; - AddressSpace *iocsr_as =3D licc->get_iocsr_as(cpu); - - if (!iocsr_as) { - return MEMTX_DECODE_ERROR; - } - - /* - * bit 27-30 is mask for byte writing, - * if the mask is 0, we need not to do anything. - */ - if ((val >> 27) & 0xf) { - data =3D address_space_ldl_le(iocsr_as, addr, attrs, NULL); - for (i =3D 0; i < 4; i++) { - /* get mask for byte writing */ - if (val & (0x1 << (27 + i))) { - mask |=3D 0xff << (i * 8); - } - } - } - - data &=3D mask; - data |=3D (val >> 32) & ~mask; - address_space_stl_le(iocsr_as, addr, data, attrs, NULL); - - return MEMTX_OK; -} - -static MemTxResult mail_send(LoongsonIPICommonState *ipi, - uint64_t val, MemTxAttrs attrs) -{ - LoongsonIPICommonClass *licc =3D LOONGSON_IPI_COMMON_GET_CLASS(ipi); - uint32_t cpuid; - hwaddr addr; - CPUState *cs; - - cpuid =3D extract32(val, 16, 10); - cs =3D licc->cpu_by_arch_id(cpuid); - if (cs =3D=3D NULL) { - return MEMTX_DECODE_ERROR; - } - - /* override requester_id */ - addr =3D SMP_IPI_MAILBOX + CORE_BUF_20 + (val & 0x1c); - attrs.requester_id =3D cs->cpu_index; - return send_ipi_data(ipi, cs, val, addr, attrs); -} - -static MemTxResult any_send(LoongsonIPICommonState *ipi, - uint64_t val, MemTxAttrs attrs) -{ - LoongsonIPICommonClass *licc =3D LOONGSON_IPI_COMMON_GET_CLASS(ipi); - uint32_t cpuid; - hwaddr addr; - CPUState *cs; - - cpuid =3D extract32(val, 16, 10); - cs =3D licc->cpu_by_arch_id(cpuid); - if (cs =3D=3D NULL) { - return MEMTX_DECODE_ERROR; - } - - /* override requester_id */ - addr =3D val & 0xffff; - attrs.requester_id =3D cs->cpu_index; - return send_ipi_data(ipi, cs, val, addr, attrs); -} - -MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, uint64_t v= al, - unsigned size, MemTxAttrs attrs) -{ - IPICore *s =3D opaque; - LoongsonIPICommonState *ipi =3D s->ipi; - LoongsonIPICommonClass *licc =3D LOONGSON_IPI_COMMON_GET_CLASS(ipi); - int index =3D 0; - uint32_t cpuid; - uint8_t vector; - CPUState *cs; - - addr &=3D 0xff; - trace_loongson_ipi_write(size, (uint64_t)addr, val); - switch (addr) { - case CORE_STATUS_OFF: - qemu_log_mask(LOG_GUEST_ERROR, "can not be written"); - break; - case CORE_EN_OFF: - s->en =3D val; - break; - case CORE_SET_OFF: - s->status |=3D val; - if (s->status !=3D 0 && (s->status & s->en) !=3D 0) { - qemu_irq_raise(s->irq); - } - break; - case CORE_CLEAR_OFF: - s->status &=3D ~val; - if (s->status =3D=3D 0 && s->en !=3D 0) { - qemu_irq_lower(s->irq); - } - break; - case CORE_BUF_20 ... CORE_BUF_38 + 4: - index =3D (addr - CORE_BUF_20) >> 2; - s->buf[index] =3D val; - break; - case IOCSR_IPI_SEND: - cpuid =3D extract32(val, 16, 10); - /* IPI status vector */ - vector =3D extract8(val, 0, 5); - cs =3D licc->cpu_by_arch_id(cpuid); - if (cs =3D=3D NULL || cs->cpu_index >=3D ipi->num_cpu) { - return MEMTX_DECODE_ERROR; - } - loongson_ipi_core_writel(&ipi->cpu[cs->cpu_index], CORE_SET_OFF, - BIT(vector), 4, attrs); - break; - default: - qemu_log_mask(LOG_UNIMP, "invalid write: %x", (uint32_t)addr); - break; - } - - return MEMTX_OK; -} - -static MemTxResult loongson_ipi_iocsr_writel(void *opaque, hwaddr addr, - uint64_t val, unsigned size, - MemTxAttrs attrs) -{ - LoongsonIPICommonState *ipi =3D opaque; - IPICore *s; - - if (attrs.requester_id >=3D ipi->num_cpu) { - return MEMTX_DECODE_ERROR; - } - - s =3D &ipi->cpu[attrs.requester_id]; - return loongson_ipi_core_writel(s, addr, val, size, attrs); -} - static const MemoryRegionOps loongson_ipi_core_ops =3D { .read_with_attrs =3D loongson_ipi_core_readl, .write_with_attrs =3D loongson_ipi_core_writel, @@ -244,88 +52,15 @@ static const MemoryRegionOps loongson_ipi_core_ops =3D= { .endianness =3D DEVICE_LITTLE_ENDIAN, }; =20 -static const MemoryRegionOps loongson_ipi_iocsr_ops =3D { - .read_with_attrs =3D loongson_ipi_iocsr_readl, - .write_with_attrs =3D loongson_ipi_iocsr_writel, - .impl.min_access_size =3D 4, - .impl.max_access_size =3D 4, - .valid.min_access_size =3D 4, - .valid.max_access_size =3D 8, - .endianness =3D DEVICE_LITTLE_ENDIAN, -}; - -/* mail send and any send only support writeq */ -static MemTxResult loongson_ipi_writeq(void *opaque, hwaddr addr, uint64_t= val, - unsigned size, MemTxAttrs attrs) -{ - LoongsonIPICommonState *ipi =3D opaque; - MemTxResult ret =3D MEMTX_OK; - - addr &=3D 0xfff; - switch (addr) { - case MAIL_SEND_OFFSET: - ret =3D mail_send(ipi, val, attrs); - break; - case ANY_SEND_OFFSET: - ret =3D any_send(ipi, val, attrs); - break; - default: - break; - } - - return ret; -} - -static const MemoryRegionOps loongson_ipi64_ops =3D { - .write_with_attrs =3D loongson_ipi_writeq, - .impl.min_access_size =3D 8, - .impl.max_access_size =3D 8, - .valid.min_access_size =3D 8, - .valid.max_access_size =3D 8, - .endianness =3D DEVICE_LITTLE_ENDIAN, -}; - -static void loongson_ipi_common_realize(DeviceState *dev, Error **errp) -{ - LoongsonIPICommonState *s =3D LOONGSON_IPI_COMMON(dev); - SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); - int i; - - if (s->num_cpu =3D=3D 0) { - error_setg(errp, "num-cpu must be at least 1"); - return; - } - - memory_region_init_io(&s->ipi_iocsr_mem, OBJECT(dev), - &loongson_ipi_iocsr_ops, - s, "loongson_ipi_iocsr", 0x48); - - /* loongson_ipi_iocsr performs re-entrant IO through ipi_send */ - s->ipi_iocsr_mem.disable_reentrancy_guard =3D true; - - sysbus_init_mmio(sbd, &s->ipi_iocsr_mem); - - memory_region_init_io(&s->ipi64_iocsr_mem, OBJECT(dev), - &loongson_ipi64_ops, - s, "loongson_ipi64_iocsr", 0x118); - sysbus_init_mmio(sbd, &s->ipi64_iocsr_mem); - - s->cpu =3D g_new0(IPICore, s->num_cpu); - for (i =3D 0; i < s->num_cpu; i++) { - s->cpu[i].ipi =3D s; - - qdev_init_gpio_out(dev, &s->cpu[i].irq, 1); - } -} - static void loongson_ipi_realize(DeviceState *dev, Error **errp) { LoongsonIPICommonState *sc =3D LOONGSON_IPI_COMMON(dev); LoongsonIPIState *s =3D LOONGSON_IPI(dev); + LoongsonIPIClass *lic =3D LOONGSON_IPI_GET_CLASS(dev); SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); Error *local_err =3D NULL; =20 - loongson_ipi_common_realize(dev, &local_err); + lic->parent_realize(dev, &local_err); if (local_err) { error_propagate(errp, local_err); return; diff --git a/hw/intc/loongson_ipi_common.c b/hw/intc/loongson_ipi_common.c index 3b9e5c943d..015f86c066 100644 --- a/hw/intc/loongson_ipi_common.c +++ b/hw/intc/loongson_ipi_common.c @@ -8,8 +8,279 @@ #include "qemu/osdep.h" #include "hw/sysbus.h" #include "hw/intc/loongson_ipi_common.h" +#include "hw/irq.h" #include "hw/qdev-properties.h" +#include "qapi/error.h" +#include "qemu/log.h" #include "migration/vmstate.h" +#include "trace.h" + +MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, uint64_t *d= ata, + unsigned size, MemTxAttrs attrs) +{ + IPICore *s =3D opaque; + uint64_t ret =3D 0; + int index =3D 0; + + addr &=3D 0xff; + switch (addr) { + case CORE_STATUS_OFF: + ret =3D s->status; + break; + case CORE_EN_OFF: + ret =3D s->en; + break; + case CORE_SET_OFF: + ret =3D 0; + break; + case CORE_CLEAR_OFF: + ret =3D 0; + break; + case CORE_BUF_20 ... CORE_BUF_38 + 4: + index =3D (addr - CORE_BUF_20) >> 2; + ret =3D s->buf[index]; + break; + default: + qemu_log_mask(LOG_UNIMP, "invalid read: %x", (uint32_t)addr); + break; + } + + trace_loongson_ipi_read(size, (uint64_t)addr, ret); + *data =3D ret; + + return MEMTX_OK; +} + +static MemTxResult loongson_ipi_iocsr_readl(void *opaque, hwaddr addr, + uint64_t *data, unsigned size, + MemTxAttrs attrs) +{ + LoongsonIPICommonState *ipi =3D opaque; + IPICore *s; + + if (attrs.requester_id >=3D ipi->num_cpu) { + return MEMTX_DECODE_ERROR; + } + + s =3D &ipi->cpu[attrs.requester_id]; + return loongson_ipi_core_readl(s, addr, data, size, attrs); +} + +static MemTxResult send_ipi_data(LoongsonIPICommonState *ipi, CPUState *cp= u, + uint64_t val, hwaddr addr, MemTxAttrs att= rs) +{ + LoongsonIPICommonClass *licc =3D LOONGSON_IPI_COMMON_GET_CLASS(ipi); + int i, mask =3D 0, data =3D 0; + AddressSpace *iocsr_as =3D licc->get_iocsr_as(cpu); + + if (!iocsr_as) { + return MEMTX_DECODE_ERROR; + } + + /* + * bit 27-30 is mask for byte writing, + * if the mask is 0, we need not to do anything. + */ + if ((val >> 27) & 0xf) { + data =3D address_space_ldl_le(iocsr_as, addr, attrs, NULL); + for (i =3D 0; i < 4; i++) { + /* get mask for byte writing */ + if (val & (0x1 << (27 + i))) { + mask |=3D 0xff << (i * 8); + } + } + } + + data &=3D mask; + data |=3D (val >> 32) & ~mask; + address_space_stl_le(iocsr_as, addr, data, attrs, NULL); + + return MEMTX_OK; +} + +static MemTxResult mail_send(LoongsonIPICommonState *ipi, + uint64_t val, MemTxAttrs attrs) +{ + LoongsonIPICommonClass *licc =3D LOONGSON_IPI_COMMON_GET_CLASS(ipi); + uint32_t cpuid; + hwaddr addr; + CPUState *cs; + + cpuid =3D extract32(val, 16, 10); + cs =3D licc->cpu_by_arch_id(cpuid); + if (cs =3D=3D NULL) { + return MEMTX_DECODE_ERROR; + } + + /* override requester_id */ + addr =3D SMP_IPI_MAILBOX + CORE_BUF_20 + (val & 0x1c); + attrs.requester_id =3D cs->cpu_index; + return send_ipi_data(ipi, cs, val, addr, attrs); +} + +static MemTxResult any_send(LoongsonIPICommonState *ipi, + uint64_t val, MemTxAttrs attrs) +{ + LoongsonIPICommonClass *licc =3D LOONGSON_IPI_COMMON_GET_CLASS(ipi); + uint32_t cpuid; + hwaddr addr; + CPUState *cs; + + cpuid =3D extract32(val, 16, 10); + cs =3D licc->cpu_by_arch_id(cpuid); + if (cs =3D=3D NULL) { + return MEMTX_DECODE_ERROR; + } + + /* override requester_id */ + addr =3D val & 0xffff; + attrs.requester_id =3D cs->cpu_index; + return send_ipi_data(ipi, cs, val, addr, attrs); +} + +MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, uint64_t v= al, + unsigned size, MemTxAttrs attrs) +{ + IPICore *s =3D opaque; + LoongsonIPICommonState *ipi =3D s->ipi; + LoongsonIPICommonClass *licc =3D LOONGSON_IPI_COMMON_GET_CLASS(ipi); + int index =3D 0; + uint32_t cpuid; + uint8_t vector; + CPUState *cs; + + addr &=3D 0xff; + trace_loongson_ipi_write(size, (uint64_t)addr, val); + switch (addr) { + case CORE_STATUS_OFF: + qemu_log_mask(LOG_GUEST_ERROR, "can not be written"); + break; + case CORE_EN_OFF: + s->en =3D val; + break; + case CORE_SET_OFF: + s->status |=3D val; + if (s->status !=3D 0 && (s->status & s->en) !=3D 0) { + qemu_irq_raise(s->irq); + } + break; + case CORE_CLEAR_OFF: + s->status &=3D ~val; + if (s->status =3D=3D 0 && s->en !=3D 0) { + qemu_irq_lower(s->irq); + } + break; + case CORE_BUF_20 ... CORE_BUF_38 + 4: + index =3D (addr - CORE_BUF_20) >> 2; + s->buf[index] =3D val; + break; + case IOCSR_IPI_SEND: + cpuid =3D extract32(val, 16, 10); + /* IPI status vector */ + vector =3D extract8(val, 0, 5); + cs =3D licc->cpu_by_arch_id(cpuid); + if (cs =3D=3D NULL || cs->cpu_index >=3D ipi->num_cpu) { + return MEMTX_DECODE_ERROR; + } + loongson_ipi_core_writel(&ipi->cpu[cs->cpu_index], CORE_SET_OFF, + BIT(vector), 4, attrs); + break; + default: + qemu_log_mask(LOG_UNIMP, "invalid write: %x", (uint32_t)addr); + break; + } + + return MEMTX_OK; +} + +static MemTxResult loongson_ipi_iocsr_writel(void *opaque, hwaddr addr, + uint64_t val, unsigned size, + MemTxAttrs attrs) +{ + LoongsonIPICommonState *ipi =3D opaque; + IPICore *s; + + if (attrs.requester_id >=3D ipi->num_cpu) { + return MEMTX_DECODE_ERROR; + } + + s =3D &ipi->cpu[attrs.requester_id]; + return loongson_ipi_core_writel(s, addr, val, size, attrs); +} + +static const MemoryRegionOps loongson_ipi_iocsr_ops =3D { + .read_with_attrs =3D loongson_ipi_iocsr_readl, + .write_with_attrs =3D loongson_ipi_iocsr_writel, + .impl.min_access_size =3D 4, + .impl.max_access_size =3D 4, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 8, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + +/* mail send and any send only support writeq */ +static MemTxResult loongson_ipi_writeq(void *opaque, hwaddr addr, uint64_t= val, + unsigned size, MemTxAttrs attrs) +{ + LoongsonIPICommonState *ipi =3D opaque; + MemTxResult ret =3D MEMTX_OK; + + addr &=3D 0xfff; + switch (addr) { + case MAIL_SEND_OFFSET: + ret =3D mail_send(ipi, val, attrs); + break; + case ANY_SEND_OFFSET: + ret =3D any_send(ipi, val, attrs); + break; + default: + break; + } + + return ret; +} + +static const MemoryRegionOps loongson_ipi64_ops =3D { + .write_with_attrs =3D loongson_ipi_writeq, + .impl.min_access_size =3D 8, + .impl.max_access_size =3D 8, + .valid.min_access_size =3D 8, + .valid.max_access_size =3D 8, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + +static void loongson_ipi_common_realize(DeviceState *dev, Error **errp) +{ + LoongsonIPICommonState *s =3D LOONGSON_IPI_COMMON(dev); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + int i; + + if (s->num_cpu =3D=3D 0) { + error_setg(errp, "num-cpu must be at least 1"); + return; + } + + memory_region_init_io(&s->ipi_iocsr_mem, OBJECT(dev), + &loongson_ipi_iocsr_ops, + s, "loongson_ipi_iocsr", 0x48); + + /* loongson_ipi_iocsr performs re-entrant IO through ipi_send */ + s->ipi_iocsr_mem.disable_reentrancy_guard =3D true; + + sysbus_init_mmio(sbd, &s->ipi_iocsr_mem); + + memory_region_init_io(&s->ipi64_iocsr_mem, OBJECT(dev), + &loongson_ipi64_ops, + s, "loongson_ipi64_iocsr", 0x118); + sysbus_init_mmio(sbd, &s->ipi64_iocsr_mem); + + s->cpu =3D g_new0(IPICore, s->num_cpu); + for (i =3D 0; i < s->num_cpu; i++) { + s->cpu[i].ipi =3D s; + + qdev_init_gpio_out(dev, &s->cpu[i].irq, 1); + } +} =20 static void loongson_ipi_common_finalize(Object *obj) { @@ -53,6 +324,7 @@ static void loongson_ipi_common_class_init(ObjectClass *= klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 + dc->realize =3D loongson_ipi_common_realize; device_class_set_props(dc, ipi_properties); dc->vmsd =3D &vmstate_loongson_ipi; } --=20 2.41.0