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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-427d2a8e420sm14059315e9.35.2024.07.18.06.20.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Jul 2024 06:20:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1721308838; x=1721913638; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=c1fMPYzgCA2DuMUlUIDYiJmgobhZB3k3qf0MZrgR6xo=; b=hNy974+eltWfo6pxlWh44OnfoccAgo9p1nG+gywIFk0c9oKZBLv8ocBnBQ/TgSGfzK 2M43BufzPD7WFFfqSXdKXy5oo498aLA9qXETx/+64ZXJd1fL2rTo90/KACSkq7OPZjK+ vK81OF3XhvKtbTXeh1MUwbeOkvgLZZ9rMmvSgF/11NsxcNKaThNWJVlQKLtodadOPJeM R58aHfp8rRItTC+CJU43csCn3Bs3odoPr5hbYgG1snMcqq6WB3vo9GBXpCmlDoDSqSQH DuhEpChIwcLPTl0BeF1WghwrxNRv8TcZPjdAmEqmk1FcdKsAekqdu8h7dm4CK8NVnMy2 +hHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721308838; x=1721913638; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=c1fMPYzgCA2DuMUlUIDYiJmgobhZB3k3qf0MZrgR6xo=; b=NibgEeXgKjfauBvRBzZ016jGKMkOZaAIZsFf+DDM2DfwYeHSuHO2FMWTxhUc2Hcnl/ DW3NhWHDzVHVIxFTsTlJZOCrYulLQoawHhg9FaZaQBRpu+S09iKFsz0H62ZvfM8d+cPH DPo/L0efT4xSiHzRxxs286W8G/l8fg+qa1ma3J+MWWfZCI3ZqPxQgElxQeIR+XlATHF7 vhTYtN8pTPubOYEOqRgoC+v1xRcYJG3bWrUjjABHCa5p8wLSJlnYsFSZAumPrEzZ32J/ kJur3pG0niDSUiQ+PewVJ/zq1BjUJBpuDYjn2Wc2ok7Lbxst5s2PutBvjcPz7lakvGrI 38mg== X-Gm-Message-State: AOJu0YzUJoSOxWqugfs9jpRc0RAVQEpTuAOle1NH0IpCrZnWhDhKkA5y rE1vE3pvldpG7jEeUvs1kJGIE3lDamZV5vZqMwWTfAHrRSPzII1/cZ2+pau+oBSmOExBBE8EA5m r X-Google-Smtp-Source: AGHT+IHFPR0b+8bziwlYILmJV5YP2neILXf5Kl5THDcQjNX+y93aDGENYEBQt2bJo217FYQpnoCqaw== X-Received: by 2002:a05:600c:4fc6:b0:426:5de3:2ae5 with SMTP id 5b1f17b1804b1-427c2cb0d7bmr39062965e9.10.1721308837814; Thu, 18 Jul 2024 06:20:37 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/26] hw/arm/smmu: Support nesting in smmuv3_range_inval() Date: Thu, 18 Jul 2024 14:20:17 +0100 Message-Id: <20240718132028.697927-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240718132028.697927-1-peter.maydell@linaro.org> References: <20240718132028.697927-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1721309022075116300 From: Mostafa Saleh With nesting, we would need to invalidate IPAs without over-invalidating stage-1 IOVAs. This can be done by distinguishing IPAs in the TLBs by having ASID=3D-1. To achieve that, rework the invalidation for IPAs to have a separate function, while for IOVA invalidation ASID=3D-1 means invalidate for all ASIDs. Reviewed-by: Eric Auger Signed-off-by: Mostafa Saleh Reviewed-by: Jean-Philippe Brucker Reviewed-by: Alex Benn=C3=A9e Message-id: 20240715084519.1189624-13-smostafa@google.com Signed-off-by: Peter Maydell --- include/hw/arm/smmu-common.h | 3 ++- hw/arm/smmu-common.c | 47 ++++++++++++++++++++++++++++++++++++ hw/arm/smmuv3.c | 23 ++++++++++++------ hw/arm/trace-events | 2 +- 4 files changed, 66 insertions(+), 9 deletions(-) diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index a51005e8b84..da9ff45fb5a 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -217,7 +217,8 @@ void smmu_iotlb_inv_asid(SMMUState *s, int asid); void smmu_iotlb_inv_vmid(SMMUState *s, int vmid); void smmu_iotlb_inv_iova(SMMUState *s, int asid, int vmid, dma_addr_t iova, uint8_t tg, uint64_t num_pages, uint8_t ttl); - +void smmu_iotlb_inv_ipa(SMMUState *s, int vmid, dma_addr_t ipa, uint8_t tg, + uint64_t num_pages, uint8_t ttl); /* Unmap the range of all the notifiers registered to any IOMMU mr */ void smmu_inv_notifiers_all(SMMUState *s); =20 diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 912b89b5eeb..4b0857ab4d7 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -195,6 +195,25 @@ static gboolean smmu_hash_remove_by_asid_vmid_iova(gpo= inter key, gpointer value, ((entry->iova & ~info->mask) =3D=3D info->iova); } =20 +static gboolean smmu_hash_remove_by_vmid_ipa(gpointer key, gpointer value, + gpointer user_data) +{ + SMMUTLBEntry *iter =3D (SMMUTLBEntry *)value; + IOMMUTLBEntry *entry =3D &iter->entry; + SMMUIOTLBPageInvInfo *info =3D (SMMUIOTLBPageInvInfo *)user_data; + SMMUIOTLBKey iotlb_key =3D *(SMMUIOTLBKey *)key; + + if (SMMU_IOTLB_ASID(iotlb_key) >=3D 0) { + /* This is a stage-1 address. */ + return false; + } + if (info->vmid !=3D SMMU_IOTLB_VMID(iotlb_key)) { + return false; + } + return ((info->iova & ~entry->addr_mask) =3D=3D entry->iova) || + ((entry->iova & ~info->mask) =3D=3D info->iova); +} + void smmu_iotlb_inv_iova(SMMUState *s, int asid, int vmid, dma_addr_t iova, uint8_t tg, uint64_t num_pages, uint8_t ttl) { @@ -223,6 +242,34 @@ void smmu_iotlb_inv_iova(SMMUState *s, int asid, int v= mid, dma_addr_t iova, &info); } =20 +/* + * Similar to smmu_iotlb_inv_iova(), but for Stage-2, ASID is always -1, + * in Stage-1 invalidation ASID =3D -1, means don't care. + */ +void smmu_iotlb_inv_ipa(SMMUState *s, int vmid, dma_addr_t ipa, uint8_t tg, + uint64_t num_pages, uint8_t ttl) +{ + uint8_t granule =3D tg ? tg * 2 + 10 : 12; + int asid =3D -1; + + if (ttl && (num_pages =3D=3D 1)) { + SMMUIOTLBKey key =3D smmu_get_iotlb_key(asid, vmid, ipa, tg, ttl); + + if (g_hash_table_remove(s->iotlb, &key)) { + return; + } + } + + SMMUIOTLBPageInvInfo info =3D { + .iova =3D ipa, + .vmid =3D vmid, + .mask =3D (num_pages << granule) - 1}; + + g_hash_table_foreach_remove(s->iotlb, + smmu_hash_remove_by_vmid_ipa, + &info); +} + void smmu_iotlb_inv_asid(SMMUState *s, int asid) { trace_smmu_iotlb_inv_asid(asid); diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 0faa08c8d8b..ebf29f3adf7 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1168,7 +1168,7 @@ static void smmuv3_inv_notifiers_iova(SMMUState *s, i= nt asid, int vmid, } } =20 -static void smmuv3_range_inval(SMMUState *s, Cmd *cmd) +static void smmuv3_range_inval(SMMUState *s, Cmd *cmd, SMMUStage stage) { dma_addr_t end, addr =3D CMD_ADDR(cmd); uint8_t type =3D CMD_TYPE(cmd); @@ -1193,9 +1193,13 @@ static void smmuv3_range_inval(SMMUState *s, Cmd *cm= d) } =20 if (!tg) { - trace_smmuv3_range_inval(vmid, asid, addr, tg, 1, ttl, leaf); + trace_smmuv3_range_inval(vmid, asid, addr, tg, 1, ttl, leaf, stage= ); smmuv3_inv_notifiers_iova(s, asid, vmid, addr, tg, 1); - smmu_iotlb_inv_iova(s, asid, vmid, addr, tg, 1, ttl); + if (stage =3D=3D SMMU_STAGE_1) { + smmu_iotlb_inv_iova(s, asid, vmid, addr, tg, 1, ttl); + } else { + smmu_iotlb_inv_ipa(s, vmid, addr, tg, 1, ttl); + } return; } =20 @@ -1211,9 +1215,14 @@ static void smmuv3_range_inval(SMMUState *s, Cmd *cm= d) uint64_t mask =3D dma_aligned_pow2_mask(addr, end, 64); =20 num_pages =3D (mask + 1) >> granule; - trace_smmuv3_range_inval(vmid, asid, addr, tg, num_pages, ttl, lea= f); + trace_smmuv3_range_inval(vmid, asid, addr, tg, num_pages, + ttl, leaf, stage); smmuv3_inv_notifiers_iova(s, asid, vmid, addr, tg, num_pages); - smmu_iotlb_inv_iova(s, asid, vmid, addr, tg, num_pages, ttl); + if (stage =3D=3D SMMU_STAGE_1) { + smmu_iotlb_inv_iova(s, asid, vmid, addr, tg, num_pages, ttl); + } else { + smmu_iotlb_inv_ipa(s, vmid, addr, tg, num_pages, ttl); + } addr +=3D mask + 1; } } @@ -1368,7 +1377,7 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) cmd_error =3D SMMU_CERROR_ILL; break; } - smmuv3_range_inval(bs, &cmd); + smmuv3_range_inval(bs, &cmd, SMMU_STAGE_1); break; case SMMU_CMD_TLBI_S12_VMALL: { @@ -1393,7 +1402,7 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) * As currently only either s1 or s2 are supported * we can reuse same function for s2. */ - smmuv3_range_inval(bs, &cmd); + smmuv3_range_inval(bs, &cmd, SMMU_STAGE_2); break; case SMMU_CMD_TLBI_EL3_ALL: case SMMU_CMD_TLBI_EL3_VA: diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 09ccd39548f..7d9c1703da1 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -46,7 +46,7 @@ smmuv3_cmdq_cfgi_ste_range(int start, int end) "start=3D0= x%x - end=3D0x%x" smmuv3_cmdq_cfgi_cd(uint32_t sid) "sid=3D0x%x" smmuv3_config_cache_hit(uint32_t sid, uint32_t hits, uint32_t misses, uint= 32_t perc) "Config cache HIT for sid=3D0x%x (hits=3D%d, misses=3D%d, hit ra= te=3D%d)" smmuv3_config_cache_miss(uint32_t sid, uint32_t hits, uint32_t misses, uin= t32_t perc) "Config cache MISS for sid=3D0x%x (hits=3D%d, misses=3D%d, hit = rate=3D%d)" -smmuv3_range_inval(int vmid, int asid, uint64_t addr, uint8_t tg, uint64_t= num_pages, uint8_t ttl, bool leaf) "vmid=3D%d asid=3D%d addr=3D0x%"PRIx64"= tg=3D%d num_pages=3D0x%"PRIx64" ttl=3D%d leaf=3D%d" +smmuv3_range_inval(int vmid, int asid, uint64_t addr, uint8_t tg, uint64_t= num_pages, uint8_t ttl, bool leaf, int stage) "vmid=3D%d asid=3D%d addr=3D= 0x%"PRIx64" tg=3D%d num_pages=3D0x%"PRIx64" ttl=3D%d leaf=3D%d stage=3D%d" smmuv3_cmdq_tlbi_nh(void) "" smmuv3_cmdq_tlbi_nh_asid(int asid) "asid=3D%d" smmuv3_cmdq_tlbi_s12_vmid(int vmid) "vmid=3D%d" --=20 2.34.1