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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-427d2a8e420sm14059315e9.35.2024.07.18.06.20.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Jul 2024 06:20:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1721308840; x=1721913640; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=VHN7yV4WQNrP5rcth7Yx1n5W3KiVohowsfOYtErcpFU=; b=VJXaVvphLY5CBlMclALVIHiHiKrLAnmX5zkoRyjd/mmK9AWoulhxPPIO5ARDxcBENj B8Rei/Sfdk5znX7CKxkLBw7sHj3By4/nd6IsTT/SnrJCqyZm0q/6LMTXnmA2PrTGmWMW GOt+YAV4EWuRmIRP6i2i6XL+A4YmCFDWb6Iv7sQZ8ZxhJvJfzVjH+30IgRd4Roui1Ca5 2puy+Yxib/brjgxShPdpgfU4Ze2WdSDJH4QXQNCY99loeOHuB0YlxMbyO1QluadgwDMr RzaldaWq9I0Hyg3PzzflhQLDaZ/0jIMLft7RQP3zmQtfsZ/uqA1y+ywymoQOxE76MRpw /v/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721308840; x=1721913640; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VHN7yV4WQNrP5rcth7Yx1n5W3KiVohowsfOYtErcpFU=; b=wdpxpUBVGLNWkyXmwKL52EJ+2AskfhTvB1Fp9NWO0/O6qeyCl8oaoeiFw7KSGq7L6t z4n8sK8a5W7840BKPfbGKOli11TnjpVA/sTSoXs440yJVJaAXi46mbQUBjFy3k4TOpgC b96N+B2tmXgBgnN3Ar6L9dhTf4JDnqwNvrd7QJox7RLmUNnRQVVBYxrmuZiY96zbRQUd x3NAlAcTvTGkzbMd/WbZTyP1+RYm6E+vVM+wxNVtqbLaLoNGRlAjgZ7SHUBvqj+nTwn2 ES3UqPm1Vk9zo1OON8+AnPRWP4gpaY5zsGo9SBDQXUfngq/gZfqkWNgMmm4KS36cfNvu 0B3Q== X-Gm-Message-State: AOJu0YzAEYSvsQGhcKZPzX7VXuLhuFamv+cTrzr8RP6GsIBJGn3zUK4/ 9Cfyr0mbMNjG1jTwFDEC1X4WS441Rj50+y7ys+9S6e98Dkbpst65DKCLTKVk1zgUSwZAfN5aDXC 6 X-Google-Smtp-Source: AGHT+IHTFeFL0/FKXZYuv0eKgw4/YmxwakVGfN7lIk3hnBat580XJutN0G9tYylfjZMPhpuP7iCm3w== X-Received: by 2002:a05:600c:1547:b0:426:593c:9351 with SMTP id 5b1f17b1804b1-427c2cc9965mr36675245e9.6.1721308840457; Thu, 18 Jul 2024 06:20:40 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/26] hw/arm/smmu: Refactor SMMU OAS Date: Thu, 18 Jul 2024 14:20:23 +0100 Message-Id: <20240718132028.697927-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240718132028.697927-1-peter.maydell@linaro.org> References: <20240718132028.697927-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1721308965938116300 From: Mostafa Saleh SMMUv3 OAS is currently hardcoded in the code to 44 bits, for nested configurations that can be a problem, as stage-2 might be shared with the CPU which might have different PARANGE, and according to SMMU manual ARM IHI 0070F.b: 6.3.6 SMMU_IDR5, OAS must match the system physical address size. This patch doesn't change the SMMU OAS, but refactors the code to make it easier to do that: - Rely everywhere on IDR5 for reading OAS instead of using the SMMU_IDR5_OAS macro, so, it is easier just to change IDR5 and it propagages correctly. - Add additional checks when OAS is greater than 48bits. - Remove unused functions/macros: pa_range/MAX_PA. Reviewed-by: Eric Auger Signed-off-by: Mostafa Saleh Reviewed-by: Jean-Philippe Brucker Reviewed-by: Alex Benn=C3=A9e Message-id: 20240715084519.1189624-19-smostafa@google.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3-internal.h | 13 ------------- hw/arm/smmu-common.c | 7 ++++--- hw/arm/smmuv3.c | 35 ++++++++++++++++++++++++++++------- 3 files changed, 32 insertions(+), 23 deletions(-) diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index 0f3ecec804d..0ebf2eebcff 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -602,19 +602,6 @@ static inline int oas2bits(int oas_field) return -1; } =20 -static inline int pa_range(STE *ste) -{ - int oas_field =3D MIN(STE_S2PS(ste), SMMU_IDR5_OAS); - - if (!STE_S2AA64(ste)) { - return 40; - } - - return oas2bits(oas_field); -} - -#define MAX_PA(ste) ((1 << pa_range(ste)) - 1) - /* CD fields */ =20 #define CD_VALID(x) extract32((x)->word[0], 31, 1) diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 00d7579cd3d..d73ad622113 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -452,7 +452,8 @@ static int smmu_ptw_64_s1(SMMUState *bs, SMMUTransCfg *= cfg, inputsize =3D 64 - tt->tsz; level =3D 4 - (inputsize - 4) / stride; indexmask =3D VMSA_IDXMSK(inputsize, stride, level); - baseaddr =3D extract64(tt->ttb, 0, 48); + + baseaddr =3D extract64(tt->ttb, 0, cfg->oas); baseaddr &=3D ~indexmask; =20 while (level < VMSA_LEVELS) { @@ -576,8 +577,8 @@ static int smmu_ptw_64_s2(SMMUTransCfg *cfg, * Get the ttb from concatenated structure. * The offset is the idx * size of each ttb(number of ptes * (sizeof(p= te)) */ - uint64_t baseaddr =3D extract64(cfg->s2cfg.vttb, 0, 48) + (1 << stride= ) * - idx * sizeof(uint64_t); + uint64_t baseaddr =3D extract64(cfg->s2cfg.vttb, 0, cfg->s2cfg.eff_ps)= + + (1 << stride) * idx * sizeof(uint64_t); dma_addr_t indexmask =3D VMSA_IDXMSK(inputsize, stride, level); =20 baseaddr &=3D ~indexmask; diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 3db6c7c1357..39719763897 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -402,10 +402,10 @@ static bool s2t0sz_valid(SMMUTransCfg *cfg) } =20 if (cfg->s2cfg.granule_sz =3D=3D 16) { - return (cfg->s2cfg.tsz >=3D 64 - oas2bits(SMMU_IDR5_OAS)); + return (cfg->s2cfg.tsz >=3D 64 - cfg->s2cfg.eff_ps); } =20 - return (cfg->s2cfg.tsz >=3D MAX(64 - oas2bits(SMMU_IDR5_OAS), 16)); + return (cfg->s2cfg.tsz >=3D MAX(64 - cfg->s2cfg.eff_ps, 16)); } =20 /* @@ -426,8 +426,11 @@ static bool s2_pgtable_config_valid(uint8_t sl0, uint8= _t t0sz, uint8_t gran) return nr_concat <=3D VMSA_MAX_S2_CONCAT; } =20 -static int decode_ste_s2_cfg(SMMUTransCfg *cfg, STE *ste) +static int decode_ste_s2_cfg(SMMUv3State *s, SMMUTransCfg *cfg, + STE *ste) { + uint8_t oas =3D FIELD_EX32(s->idr[5], IDR5, OAS); + if (STE_S2AA64(ste) =3D=3D 0x0) { qemu_log_mask(LOG_UNIMP, "SMMUv3 AArch32 tables not supported\n"); @@ -460,7 +463,15 @@ static int decode_ste_s2_cfg(SMMUTransCfg *cfg, STE *s= te) } =20 /* For AA64, The effective S2PS size is capped to the OAS. */ - cfg->s2cfg.eff_ps =3D oas2bits(MIN(STE_S2PS(ste), SMMU_IDR5_OAS)); + cfg->s2cfg.eff_ps =3D oas2bits(MIN(STE_S2PS(ste), oas)); + /* + * For SMMUv3.1 and later, when OAS =3D=3D IAS =3D=3D 52, the stage 2 = input + * range is further limited to 48 bits unless STE.S2TG indicates a + * 64KB granule. + */ + if (cfg->s2cfg.granule_sz !=3D 16) { + cfg->s2cfg.eff_ps =3D MIN(cfg->s2cfg.eff_ps, 48); + } /* * It is ILLEGAL for the address in S2TTB to be outside the range * described by the effective S2PS value. @@ -536,6 +547,7 @@ static int decode_ste(SMMUv3State *s, SMMUTransCfg *cfg, STE *ste, SMMUEventInfo *event) { uint32_t config; + uint8_t oas =3D FIELD_EX32(s->idr[5], IDR5, OAS); int ret; =20 if (!STE_VALID(ste)) { @@ -579,8 +591,8 @@ static int decode_ste(SMMUv3State *s, SMMUTransCfg *cfg, * Stage-1 OAS defaults to OAS even if not enabled as it would be = used * in input address check for stage-2. */ - cfg->oas =3D oas2bits(SMMU_IDR5_OAS); - ret =3D decode_ste_s2_cfg(cfg, ste); + cfg->oas =3D oas2bits(oas); + ret =3D decode_ste_s2_cfg(s, cfg, ste); if (ret) { goto bad_ste; } @@ -706,6 +718,7 @@ static int decode_cd(SMMUv3State *s, SMMUTransCfg *cfg, int i; SMMUTranslationStatus status; SMMUTLBEntry *entry; + uint8_t oas =3D FIELD_EX32(s->idr[5], IDR5, OAS); =20 if (!CD_VALID(cd) || !CD_AARCH64(cd)) { goto bad_cd; @@ -724,7 +737,7 @@ static int decode_cd(SMMUv3State *s, SMMUTransCfg *cfg, cfg->aa64 =3D true; =20 cfg->oas =3D oas2bits(CD_IPS(cd)); - cfg->oas =3D MIN(oas2bits(SMMU_IDR5_OAS), cfg->oas); + cfg->oas =3D MIN(oas2bits(oas), cfg->oas); cfg->tbi =3D CD_TBI(cd); cfg->asid =3D CD_ASID(cd); cfg->affd =3D CD_AFFD(cd); @@ -753,6 +766,14 @@ static int decode_cd(SMMUv3State *s, SMMUTransCfg *cfg, goto bad_cd; } =20 + /* + * An address greater than 48 bits in size can only be output from= a + * TTD when, in SMMUv3.1 and later, the effective IPS is 52 and a = 64KB + * granule is in use for that translation table + */ + if (tt->granule_sz !=3D 16) { + cfg->oas =3D MIN(cfg->oas, 48); + } tt->tsz =3D tsz; tt->ttb =3D CD_TTB(cd, i); =20 --=20 2.34.1