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envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::441; envelope-from=luzhixing12345@gmail.com; helo=mail-pf1-x441.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1721365111870116300 Content-Type: text/plain; charset="utf-8" Add more information with CXL type1 and type2 devices. Original doc says "May also have device private memory accessible=20 via means such as PCI memory reads and writes to BARs.", but actually CXL type1 devices doesn't have device memory. Signed-off-by: luzhixing12345 --- docs/system/devices/cxl.rst | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst index 882b036f5e..ee50a3c18d 100644 --- a/docs/system/devices/cxl.rst +++ b/docs/system/devices/cxl.rst @@ -46,20 +46,14 @@ CXL 2.0 Device Types -------------------- CXL 2.0 End Points are often categorized into three types. =20 -**Type 1:** These support coherent caching of host memory. Example might -be a crypto accelerators. May also have device private memory accessible -via means such as PCI memory reads and writes to BARs. +**Type 1: Accelerators without device memory**. These support coherent cac= hing of host memory. Example might be a crypto accelerators or smart NICs t= hat use coherency semantics along with PCIe-style DMA transfers. Type1 devi= ces implement a fully coherent cache but no host-managed device memory. =20 -**Type 2:** These support coherent caching of host memory and host -managed device memory (HDM) for which the coherency protocol is managed -by the host. This is a complex topic, so for more information on CXL -coherency see the CXL 2.0 specification. +**Type 2: Accelerators with device memory**. These support coherent cachin= g of host memory and host managed device memory (HDM) for which the coheren= cy protocol is managed by the host. Type 2 devices are accelerators such as= GP-GPUs and FPGAs with device memory that can be mapped in part to the cac= heable system memory. These devices also cache system memory for processing. =20 -**Type 3 Memory devices:** These devices act as a means of attaching -additional memory (HDM) to a CXL host including both volatile and -persistent memory. The CXL topology may support interleaving across a -number of Type 3 memory devices using HDM Decoders in the host, host -bridge, switch upstream port and endpoints. +**Type 3: Memory devices**. These devices act as a means of attaching +additional memory (HDM) to a CXL host with different memory types, includi= ng supporting multiple memory tiers attached to the device with both volati= le and persistent memory. The CXL topology may support interleaving across = a number of Type 3 memory devices using HDM Decoders in the host, host brid= ge, switch upstream port and endpoints. + +See more information about CXL.io CXL.cache CXL.mem in the `CXL 2.0 specif= ication `_. =20 Scope of CXL emulation in QEMU ------------------------------ --=20 2.34.1