From nobody Thu Sep 19 01:10:15 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.alibaba.com ARC-Seal: i=1; a=rsa-sha256; t=1721431047; cv=none; d=zohomail.com; s=zohoarc; b=Gq4pn4L7Ui7lQIXu2PnceV57hsn3ngSCKm+4kFeJh0pMYkRjyz3gAqHIC0NcYsHaVKs1l8fpQDQUWDXME64emIiq0/Csgt+mV1vsK5mFzcZ3JR8mTFFEZ/f4FTH3xwqJt/rhd7BfD5bxww1oJ+GvtSuieNiGTKlxybM6n8SOyRE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1721431047; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=X5zGpxLFDP6TZmPG9gBGxVjxdH3PDI/fPJCAlb5f8bI=; b=fczSwkUCG5nepD/1V6TQjksZT41Co/Vrtj5z6GKlwi75bsSn7INsJjQFt7BKabpnujZdIzjihd0ekyg0PJsag2hUrljcdjbv9ALyvUUP1XpHjJzucgF1JhjbCEYKq/biIMW9OhwJyJDajnqG7B3RAdft4KzWh7eBUiF90BLONkY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1721431047420833.6803220394255; Fri, 19 Jul 2024 16:17:27 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sUwqj-0001y9-UF; Fri, 19 Jul 2024 19:17:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sUwqi-0001tq-R5; Fri, 19 Jul 2024 19:17:16 -0400 Received: from out30-110.freemail.mail.aliyun.com ([115.124.30.110]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sUwqg-0006MR-FI; Fri, 19 Jul 2024 19:17:16 -0400 Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@linux.alibaba.com fp:SMTPD_---0WAskmxx_1721431028) by smtp.aliyun-inc.com; Sat, 20 Jul 2024 07:17:09 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1721431030; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=X5zGpxLFDP6TZmPG9gBGxVjxdH3PDI/fPJCAlb5f8bI=; b=yTUPY6+EesTpxkWqTcj2BHQ6fKqgJk00YJuxfF3+M7doC6yf0Qj9j6qO/i6BRp1tMAbhATrgDp3QDelG7G15I78znWBYlHwp+r1bHEmePStqNRx/k7Pn2PVZyxyfQl5T3BKAljwQyzmVo5brEJ/xl+FBTsKyy0Yl30fzApUa7Zw= X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R861e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=maildocker-contentspam033037067110; MF=zhiwei_liu@linux.alibaba.com; NM=1; PH=DS; RN=11; SR=0; TI=SMTPD_---0WAskmxx_1721431028; From: LIU Zhiwei To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, zhiwei_liu@linux.alibaba.com, philmd@linaro.org, alex.bennee@linaro.org, TANG Tiancheng Subject: [PATCH v6 5/8] target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU Date: Sat, 20 Jul 2024 07:11:46 +0800 Message-Id: <20240719231149.1364-6-zhiwei_liu@linux.alibaba.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20240719231149.1364-1-zhiwei_liu@linux.alibaba.com> References: <20240719231149.1364-1-zhiwei_liu@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=115.124.30.110; envelope-from=zhiwei_liu@linux.alibaba.com; helo=out30-110.freemail.mail.aliyun.com X-Spam_score_int: -174 X-Spam_score: -17.5 X-Spam_bar: ----------------- X-Spam_report: (-17.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.alibaba.com) X-ZM-MESSAGEID: 1721431049675116300 Content-Type: text/plain; charset="utf-8" From: TANG Tiancheng Ensure mcause high bit is correctly set by using 32-bit width for RV32 mode and 64-bit width for RV64 mode. Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu_helper.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 4f0ab90ac7..3eedb26cd9 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1673,6 +1673,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) target_ulong tinst =3D 0; target_ulong htval =3D 0; target_ulong mtval2 =3D 0; + int sxlen =3D 0; + int mxlen =3D 0; =20 if (!async) { /* set tval to badaddr for traps with address information */ @@ -1799,7 +1801,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) s =3D set_field(s, MSTATUS_SPP, env->priv); s =3D set_field(s, MSTATUS_SIE, 0); env->mstatus =3D s; - env->scause =3D cause | ((target_ulong)async << (TARGET_LONG_BITS = - 1)); + sxlen =3D 16 << riscv_cpu_sxl(env); + env->scause =3D cause | ((target_ulong)async << (sxlen - 1)); env->sepc =3D env->pc; env->stval =3D tval; env->htval =3D htval; @@ -1830,7 +1833,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) s =3D set_field(s, MSTATUS_MPP, env->priv); s =3D set_field(s, MSTATUS_MIE, 0); env->mstatus =3D s; - env->mcause =3D cause | ~(((target_ulong)-1) >> async); + mxlen =3D 16 << riscv_cpu_mxl(env); + env->mcause =3D cause | ((target_ulong)async << (mxlen - 1)); env->mepc =3D env->pc; env->mtval =3D tval; env->mtval2 =3D mtval2; --=20 2.25.1