From nobody Thu Sep 19 01:42:51 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.alibaba.com ARC-Seal: i=1; a=rsa-sha256; t=1721431116; cv=none; d=zohomail.com; s=zohoarc; b=LBQJ6RIm7R89Nh396dT1mgWVFkmX9+8hOr9MVeC5GZVvrOLySfvNa3lRzn4Hp/o6NFc9utHUPDXm6z9hj0HE1HcK9QE8aGoFQLYhQYu7EEs/WzgiVTgQmo+qeoZf1p12mHOXrLZzqMmBg4/pgdtXQoc/q0EQ/Zl6IQyCP1ZpCKk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1721431116; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=mQk+HoZF2f0RtHDlald+dinWdqte5kUK2h4GqQ4FmQY=; b=INSTAZ8eXt7f0RNO3ETcBiPvrVNhGPXso7EYngJhqIaFCRIqcLuadqFiJFokaHp2EC4aSjjAuo5pDpKHRhn1JdGGSKZTo+4Q79v2Wyv+BugQ5cfha/j3YCQwuVHnWAhogFu30U2cere4OeLTUy7bTR8KVf1Kl0sWMu3XR8dJSzI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17214311161881007.6581595145489; Fri, 19 Jul 2024 16:18:36 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sUwrj-0006ym-Kf; Fri, 19 Jul 2024 19:18:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sUwri-0006u6-Cs; Fri, 19 Jul 2024 19:18:18 -0400 Received: from out30-130.freemail.mail.aliyun.com ([115.124.30.130]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sUwrg-0006RR-Nl; Fri, 19 Jul 2024 19:18:18 -0400 Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@linux.alibaba.com fp:SMTPD_---0WAsnMN0_1721431091) by smtp.aliyun-inc.com; Sat, 20 Jul 2024 07:18:12 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1721431093; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=mQk+HoZF2f0RtHDlald+dinWdqte5kUK2h4GqQ4FmQY=; b=I0vjNj3MBJ5/kMU8wTqquA+LsPpXXa/9WqZVewvH2Scz/6Kmo7oZ6UUJVQJzWCTXXaDipCeyBkFhv7pEYN9mFOv46MPO2GXzTgqUM5zpELvCzbz2DSrBpoa0UHEDJ/lsLjxsGZ0XJJ0/E0hWeulhIsdjkZq3TvpGfl7vvil4SZw= X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R671e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=maildocker-contentspam033045046011; MF=zhiwei_liu@linux.alibaba.com; NM=1; PH=DS; RN=10; SR=0; TI=SMTPD_---0WAsnMN0_1721431091; From: LIU Zhiwei To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, zhiwei_liu@linux.alibaba.com, philmd@linaro.org, alex.bennee@linaro.org Subject: [PATCH v6 7/8] target/riscv: Add any32 and max32 CPU for RV64 QEMU Date: Sat, 20 Jul 2024 07:11:48 +0800 Message-Id: <20240719231149.1364-8-zhiwei_liu@linux.alibaba.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20240719231149.1364-1-zhiwei_liu@linux.alibaba.com> References: <20240719231149.1364-1-zhiwei_liu@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=115.124.30.130; envelope-from=zhiwei_liu@linux.alibaba.com; helo=out30-130.freemail.mail.aliyun.com X-Spam_score_int: -174 X-Spam_score: -17.5 X-Spam_bar: ----------------- X-Spam_report: (-17.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.alibaba.com) X-ZM-MESSAGEID: 1721431117756116300 Content-Type: text/plain; charset="utf-8" We may need 32-bit max or 32-bit any CPU for RV64 QEMU. Thus we add these two CPUs for RV64 QEMU. The reason we don't expose them to RV32 QEMU is that we already have max or any cpu with the same configuration. Another reason is that we want to follow the RISC-V custom where addw instruction doesn't exist in RV32 CPU. Signed-off-by: LIU Zhiwei Suggested-by: Daniel Henrique Barboza Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu-qom.h | 2 ++ target/riscv/cpu.c | 13 ++++++++----- 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index 3670cfe6d9..9f91743b78 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -31,6 +31,8 @@ =20 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") #define TYPE_RISCV_CPU_MAX RISCV_CPU_TYPE_NAME("max") +#define TYPE_RISCV_CPU_ANY32 RISCV_CPU_TYPE_NAME("any32") +#define TYPE_RISCV_CPU_MAX32 RISCV_CPU_TYPE_NAME("max32") #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0df145d90f..ab2512bb19 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -464,11 +464,9 @@ static void riscv_max_cpu_init(Object *obj) =20 env->priv_ver =3D PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY -#ifdef TARGET_RISCV32 - set_satp_mode_max_supported(cpu, VM_1_10_SV32); -#else - set_satp_mode_max_supported(cpu, VM_1_10_SV57); -#endif + set_satp_mode_max_supported(RISCV_CPU(obj), + riscv_cpu_mxl(&RISCV_CPU(obj)->env) =3D=3D MXL_RV32 ? + VM_1_10_SV32 : VM_1_10_SV57); #endif } =20 @@ -2962,6 +2960,11 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV32E, MXL_RV32, rv32e_bare_cpu= _init), #endif =20 +#if (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY)) + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY32, MXL_RV32, riscv_any_cpu_= init), + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX32, MXL_RV32, riscv_max_cpu_= init), +#endif + #if defined(TARGET_RISCV64) DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, MXL_RV64, rv64_base_cpu_= init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E51, MXL_RV64, rv64_sifive_e_= cpu_init), --=20 2.25.1