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envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=7863c9c60=alistair.francis@wdc.com; helo=esa1.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" We don't need to expose the register layout in the public header, so don't. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng --- include/hw/char/ibex_uart.h | 37 ------------------------------------- hw/char/ibex_uart.c | 37 +++++++++++++++++++++++++++++++++++++ 2 files changed, 37 insertions(+), 37 deletions(-) diff --git a/include/hw/char/ibex_uart.h b/include/hw/char/ibex_uart.h index 546f958eb8..a39985516a 100644 --- a/include/hw/char/ibex_uart.h +++ b/include/hw/char/ibex_uart.h @@ -31,43 +31,6 @@ #include "qemu/timer.h" #include "qom/object.h" =20 -REG32(INTR_STATE, 0x00) - FIELD(INTR_STATE, TX_WATERMARK, 0, 1) - FIELD(INTR_STATE, RX_WATERMARK, 1, 1) - FIELD(INTR_STATE, TX_EMPTY, 2, 1) - FIELD(INTR_STATE, RX_OVERFLOW, 3, 1) -REG32(INTR_ENABLE, 0x04) -REG32(INTR_TEST, 0x08) -REG32(CTRL, 0x0C) - FIELD(CTRL, TX_ENABLE, 0, 1) - FIELD(CTRL, RX_ENABLE, 1, 1) - FIELD(CTRL, NF, 2, 1) - FIELD(CTRL, SLPBK, 4, 1) - FIELD(CTRL, LLPBK, 5, 1) - FIELD(CTRL, PARITY_EN, 6, 1) - FIELD(CTRL, PARITY_ODD, 7, 1) - FIELD(CTRL, RXBLVL, 8, 2) - FIELD(CTRL, NCO, 16, 16) -REG32(STATUS, 0x10) - FIELD(STATUS, TXFULL, 0, 1) - FIELD(STATUS, RXFULL, 1, 1) - FIELD(STATUS, TXEMPTY, 2, 1) - FIELD(STATUS, RXIDLE, 4, 1) - FIELD(STATUS, RXEMPTY, 5, 1) -REG32(RDATA, 0x14) -REG32(WDATA, 0x18) -REG32(FIFO_CTRL, 0x1c) - FIELD(FIFO_CTRL, RXRST, 0, 1) - FIELD(FIFO_CTRL, TXRST, 1, 1) - FIELD(FIFO_CTRL, RXILVL, 2, 3) - FIELD(FIFO_CTRL, TXILVL, 5, 2) -REG32(FIFO_STATUS, 0x20) - FIELD(FIFO_STATUS, TXLVL, 0, 5) - FIELD(FIFO_STATUS, RXLVL, 16, 5) -REG32(OVRD, 0x24) -REG32(VAL, 0x28) -REG32(TIMEOUT_CTRL, 0x2c) - #define IBEX_UART_TX_FIFO_SIZE 16 #define IBEX_UART_CLOCK 50000000 /* 50MHz clock */ =20 diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c index 73b8f2e45b..fe4b6c3c9e 100644 --- a/hw/char/ibex_uart.c +++ b/hw/char/ibex_uart.c @@ -35,6 +35,43 @@ #include "qemu/log.h" #include "qemu/module.h" =20 +REG32(INTR_STATE, 0x00) + FIELD(INTR_STATE, TX_WATERMARK, 0, 1) + FIELD(INTR_STATE, RX_WATERMARK, 1, 1) + FIELD(INTR_STATE, TX_EMPTY, 2, 1) + FIELD(INTR_STATE, RX_OVERFLOW, 3, 1) +REG32(INTR_ENABLE, 0x04) +REG32(INTR_TEST, 0x08) +REG32(CTRL, 0x0C) + FIELD(CTRL, TX_ENABLE, 0, 1) + FIELD(CTRL, RX_ENABLE, 1, 1) + FIELD(CTRL, NF, 2, 1) + FIELD(CTRL, SLPBK, 4, 1) + FIELD(CTRL, LLPBK, 5, 1) + FIELD(CTRL, PARITY_EN, 6, 1) + FIELD(CTRL, PARITY_ODD, 7, 1) + FIELD(CTRL, RXBLVL, 8, 2) + FIELD(CTRL, NCO, 16, 16) +REG32(STATUS, 0x10) + FIELD(STATUS, TXFULL, 0, 1) + FIELD(STATUS, RXFULL, 1, 1) + FIELD(STATUS, TXEMPTY, 2, 1) + FIELD(STATUS, RXIDLE, 4, 1) + FIELD(STATUS, RXEMPTY, 5, 1) +REG32(RDATA, 0x14) +REG32(WDATA, 0x18) +REG32(FIFO_CTRL, 0x1c) + FIELD(FIFO_CTRL, RXRST, 0, 1) + FIELD(FIFO_CTRL, TXRST, 1, 1) + FIELD(FIFO_CTRL, RXILVL, 2, 3) + FIELD(FIFO_CTRL, TXILVL, 5, 2) +REG32(FIFO_STATUS, 0x20) + FIELD(FIFO_STATUS, TXLVL, 0, 5) + FIELD(FIFO_STATUS, RXLVL, 16, 5) +REG32(OVRD, 0x24) +REG32(VAL, 0x28) +REG32(TIMEOUT_CTRL, 0x2c) + static void ibex_uart_update_irqs(IbexUartState *s) { if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_TX_WATERMA= RK_MASK) { --=20 2.31.1 From nobody Tue May 7 04:13:01 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; 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IronPort-SDR: 9/nFd5UUyTQZJz4UDyNV+YZlFwPOmYW5pKUVdAfmlFvNWFO6xRat8R84FHE0fNuD3Rd+aNztxe k8jx5rh+3NGu7sidbA6Qk1R3X8gZGJwyab5dRt66tkFcjLZgCt6Z+O3k0wO64PE8tfHiF176BU 8TY8Z87b/Gx/Mh1/CgAVfjVuXncm+SfDNNind4UtRLuLGj9k1g7CqMLA7IbJ8oCcz06oVgOIY6 swRcHV8RND3crX/obkZDrKwPk8R8kKHsFc5K/c6iJWTohXY6GutxOhNWazViz+mHXnmyp+T+2E jyE= X-IronPort-AV: E=Sophos;i="5.83,259,1616428800"; d="scan'208";a="282652330" IronPort-SDR: Qbq9FCFf3r2s7mpOum7Z47M2pzRi2UiHxIPwgmguLwcD0D9ncibnYwsPbjFt7rUp8ddh0GheWG yI4Y6e0Q4W9dgrDCW8B8pcc/iZN5HAcQyeXT/83/w7CPfRrihCSjyXNs0zGGA9VAbryOB+oI/T WJtO93zfg/IeCXvr6cpxK+xOnfECbyooq+pGV3FhBGgew6EU7otQzmhHto96Fk2MePcCcMP+vm fx11rRDeZEJssFUbAP6BHSnXF1kMdpE8fiOs5luBa/j/QuuhsK/FvHsjOdVr+Y17HBH+/eY083 MmsQBauF8shrhrWoXrjYUdU9 IronPort-SDR: 3VdOQjI85jErE/rmbDS+FCFOOR4ANopn49j6WIJzdi00J6d2/ab4lac4+jbU0L1HQMQpmbF2cp KfarETz15shkM00IYr83oIs2nsFGhpTe9Dete8JyapCYLcEDRjQVPV9+e6uintR/nE6nzO0ljp D5SCOkqZEQ/+N0h3NNkKejbo5zRv/nsLHYhBZdMVuqqTReNubxpNq820XC29tum6VoyRpsY6HA yGQGT+k7ALWa1FrWdnEgO1l+9+eI6G6IfCvIQmATaQhldrzp/IxWMkbZEqAgqQ0PV3rRHhRh9u hzI= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 2/3] hw/timer: Initial commit of Ibex Timer Date: Wed, 9 Jun 2021 09:48:55 +1000 Message-Id: X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=7863c9c60=alistair.francis@wdc.com; helo=esa1.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Add support for the Ibex timer. This is used with the RISC-V mtime/mtimecmp similar to the SiFive CLINT. We currently don't support changing the prescale or the timervalue. Signed-off-by: Alistair Francis --- include/hw/timer/ibex_timer.h | 52 ++++++ hw/timer/ibex_timer.c | 305 ++++++++++++++++++++++++++++++++++ MAINTAINERS | 6 +- hw/timer/meson.build | 1 + 4 files changed, 360 insertions(+), 4 deletions(-) create mode 100644 include/hw/timer/ibex_timer.h create mode 100644 hw/timer/ibex_timer.c diff --git a/include/hw/timer/ibex_timer.h b/include/hw/timer/ibex_timer.h new file mode 100644 index 0000000000..6a43537003 --- /dev/null +++ b/include/hw/timer/ibex_timer.h @@ -0,0 +1,52 @@ +/* + * QEMU lowRISC Ibex Timer device + * + * Copyright (c) 2021 Western Digital + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#ifndef HW_IBEX_TIMER_H +#define HW_IBEX_TIMER_H + +#include "hw/sysbus.h" + +#define TYPE_IBEX_TIMER "ibex-timer" +OBJECT_DECLARE_SIMPLE_TYPE(IbexTimerState, IBEX_TIMER) + +struct IbexTimerState { + /* */ + SysBusDevice parent_obj; + + /* */ + MemoryRegion mmio; + + uint32_t timer_ctrl; + uint32_t timer_cfg0; + uint32_t timer_compare_lower0; + uint32_t timer_compare_upper0; + uint32_t timer_intr_enable; + uint32_t timer_intr_state; + uint32_t timer_intr_test; + + uint32_t timebase_freq; + + qemu_irq irq; +}; +#endif /* HW_IBEX_TIMER_H */ diff --git a/hw/timer/ibex_timer.c b/hw/timer/ibex_timer.c new file mode 100644 index 0000000000..4d55eb5088 --- /dev/null +++ b/hw/timer/ibex_timer.c @@ -0,0 +1,305 @@ +/* + * QEMU lowRISC Ibex Timer device + * + * Copyright (c) 2021 Western Digital + * + * For details check the documentation here: + * https://docs.opentitan.org/hw/ip/rv_timer/doc/ + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/timer.h" +#include "hw/timer/ibex_timer.h" +#include "hw/irq.h" +#include "hw/qdev-properties.h" +#include "target/riscv/cpu.h" +#include "migration/vmstate.h" + +REG32(CTRL, 0x00) + FIELD(CTRL, ACTIVE, 0, 1) +REG32(CFG0, 0x100) + FIELD(CFG0, PRESCALE, 0, 12) + FIELD(CFG0, STEP, 16, 8) +REG32(LOWER0, 0x104) +REG32(UPPER0, 0x108) +REG32(COMPARE_LOWER0, 0x10C) +REG32(COMPARE_UPPER0, 0x110) +REG32(INTR_ENABLE, 0x114) + FIELD(INTR_ENABLE, IE_0, 0, 1) +REG32(INTR_STATE, 0x118) + FIELD(INTR_STATE, IS_0, 0, 1) +REG32(INTR_TEST, 0x11C) + FIELD(INTR_TEST, T_0, 0, 1) + +static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq) +{ + return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), + timebase_freq, NANOSECONDS_PER_SECOND); +} + +static void ibex_timer_update_irqs(IbexTimerState *s) +{ + CPUState *cs =3D qemu_get_cpu(0); + RISCVCPU *cpu =3D RISCV_CPU(cs); + uint64_t value =3D s->timer_compare_lower0 | + ((uint64_t)s->timer_compare_upper0 << 32); + uint64_t next, diff; + uint64_t now =3D cpu_riscv_read_rtc(s->timebase_freq); + + if (!(s->timer_ctrl & R_CTRL_ACTIVE_MASK)) { + /* Timer isn't active */ + return; + } + + /* Update the CPUs mtimecmp */ + cpu->env.timecmp =3D value; + + if (cpu->env.timecmp <=3D now) { + /* + * If the mtimecmp was in the past raise the interrupt now. + */ + riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(1)); + if (s->timer_intr_enable & R_INTR_ENABLE_IE_0_MASK) { + s->timer_intr_state |=3D R_INTR_STATE_IS_0_MASK; + qemu_set_irq(s->irq, true); + } + return; + } + + /* Setup a timer to trigger the interrupt in the future */ + riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(0)); + qemu_set_irq(s->irq, false); + + diff =3D cpu->env.timecmp - now; + next =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + + muldiv64(diff, + NANOSECONDS_PER_SECOND, + s->timebase_freq); + + if (next < qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) { + /* We overflowed the timer, just set it as large as we can */ + timer_mod(cpu->env.timer, 0x07FFFFFFFFFFFFFF); + } else { + timer_mod(cpu->env.timer, next); + } +} + +static void ibex_timer_cb(void *opaque) +{ + IbexTimerState *s =3D opaque; + CPUState *cs =3D qemu_get_cpu(0); + RISCVCPU *cpu =3D RISCV_CPU(cs); + + riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(1)); + if (s->timer_intr_enable & R_INTR_ENABLE_IE_0_MASK) { + s->timer_intr_state |=3D R_INTR_STATE_IS_0_MASK; + qemu_set_irq(s->irq, true); + } +} + +static void ibex_timer_reset(DeviceState *dev) +{ + IbexTimerState *s =3D IBEX_TIMER(dev); + + CPUState *cpu =3D qemu_get_cpu(0); + CPURISCVState *env =3D cpu->env_ptr; + env->timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, + &ibex_timer_cb, s); + env->timecmp =3D 0; + + s->timer_ctrl =3D 0x00000000; + s->timer_cfg0 =3D 0x00010000; + s->timer_compare_lower0 =3D 0xFFFFFFFF; + s->timer_compare_upper0 =3D 0xFFFFFFFF; + s->timer_intr_enable =3D 0x00000000; + s->timer_intr_state =3D 0x00000000; + s->timer_intr_test =3D 0x00000000; + + ibex_timer_update_irqs(s); +} + +static uint64_t ibex_timer_read(void *opaque, hwaddr addr, + unsigned int size) +{ + IbexTimerState *s =3D opaque; + uint64_t now =3D cpu_riscv_read_rtc(s->timebase_freq); + uint64_t retvalue =3D 0; + + switch (addr >> 2) { + case R_CTRL: + retvalue =3D s->timer_ctrl; + break; + case R_CFG0: + retvalue =3D s->timer_cfg0; + break; + case R_LOWER0: + retvalue =3D now; + break; + case R_UPPER0: + retvalue =3D now >> 32; + break; + case R_COMPARE_LOWER0: + retvalue =3D s->timer_compare_lower0; + break; + case R_COMPARE_UPPER0: + retvalue =3D s->timer_compare_upper0; + break; + case R_INTR_ENABLE: + retvalue =3D s->timer_intr_enable; + break; + case R_INTR_STATE: + retvalue =3D s->timer_intr_state; + break; + case R_INTR_TEST: + retvalue =3D s->timer_intr_test; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); + return 0; + } + + return retvalue; +} + +static void ibex_timer_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + IbexTimerState *s =3D opaque; + uint32_t val =3D val64; + + switch (addr >> 2) { + case R_CTRL: + s->timer_ctrl =3D val; + break; + case R_CFG0: + qemu_log_mask(LOG_UNIMP, "Changing prescale or step not supported"= ); + s->timer_cfg0 =3D val; + break; + case R_LOWER0: + qemu_log_mask(LOG_UNIMP, "Changing timer value is not supported"); + break; + case R_UPPER0: + qemu_log_mask(LOG_UNIMP, "Changing timer value is not supported"); + break; + case R_COMPARE_LOWER0: + s->timer_compare_lower0 =3D val; + ibex_timer_update_irqs(s); + break; + case R_COMPARE_UPPER0: + s->timer_compare_upper0 =3D val; + ibex_timer_update_irqs(s); + break; + case R_INTR_ENABLE: + s->timer_intr_enable =3D val; + break; + case R_INTR_STATE: + /* Write 1 to clear */ + s->timer_intr_state &=3D ~val; + break; + case R_INTR_TEST: + s->timer_intr_test =3D val; + if (s->timer_intr_enable & + s->timer_intr_test & + R_INTR_ENABLE_IE_0_MASK) { + s->timer_intr_state |=3D R_INTR_STATE_IS_0_MASK; + qemu_set_irq(s->irq, true); + } + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); + } +} + +static const MemoryRegionOps ibex_timer_ops =3D { + .read =3D ibex_timer_read, + .write =3D ibex_timer_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .impl.min_access_size =3D 4, + .impl.max_access_size =3D 4, +}; + +static int ibex_timer_post_load(void *opaque, int version_id) +{ + IbexTimerState *s =3D opaque; + + ibex_timer_update_irqs(s); + return 0; +} + +static const VMStateDescription vmstate_ibex_timer =3D { + .name =3D TYPE_IBEX_TIMER, + .version_id =3D 1, + .minimum_version_id =3D 1, + .post_load =3D ibex_timer_post_load, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32(timer_ctrl, IbexTimerState), + VMSTATE_UINT32(timer_cfg0, IbexTimerState), + VMSTATE_UINT32(timer_compare_lower0, IbexTimerState), + VMSTATE_UINT32(timer_compare_upper0, IbexTimerState), + VMSTATE_UINT32(timer_intr_enable, IbexTimerState), + VMSTATE_UINT32(timer_intr_state, IbexTimerState), + VMSTATE_UINT32(timer_intr_test, IbexTimerState), + VMSTATE_END_OF_LIST() + } +}; + +static Property ibex_timer_properties[] =3D { + DEFINE_PROP_UINT32("timebase-freq", IbexTimerState, timebase_freq, 100= 00), + DEFINE_PROP_END_OF_LIST(), +}; + +static void ibex_timer_init(Object *obj) +{ + IbexTimerState *s =3D IBEX_TIMER(obj); + + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); + + memory_region_init_io(&s->mmio, obj, &ibex_timer_ops, s, + TYPE_IBEX_TIMER, 0x400); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); +} + +static void ibex_timer_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->reset =3D ibex_timer_reset; + dc->vmsd =3D &vmstate_ibex_timer; + device_class_set_props(dc, ibex_timer_properties); +} + +static const TypeInfo ibex_timer_info =3D { + .name =3D TYPE_IBEX_TIMER, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(IbexTimerState), + .instance_init =3D ibex_timer_init, + .class_init =3D ibex_timer_class_init, +}; + +static void ibex_timer_register_types(void) +{ + type_register_static(&ibex_timer_info); +} + +type_init(ibex_timer_register_types) diff --git a/MAINTAINERS b/MAINTAINERS index 7d9cd29042..b661c9c14e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1363,11 +1363,9 @@ M: Alistair Francis L: qemu-riscv@nongnu.org S: Supported F: hw/riscv/opentitan.c -F: hw/char/ibex_uart.c -F: hw/intc/ibex_plic.c +F: hw/*/ibex_*.c F: include/hw/riscv/opentitan.h -F: include/hw/char/ibex_uart.h -F: include/hw/intc/ibex_plic.h +F: include/hw/*/ibex_*.h =20 Microchip PolarFire SoC Icicle Kit M: Bin Meng diff --git a/hw/timer/meson.build b/hw/timer/meson.build index 157f540ecd..1aa3cd2284 100644 --- a/hw/timer/meson.build +++ b/hw/timer/meson.build @@ -33,5 +33,6 @@ softmmu_ss.add(when: 'CONFIG_SSE_COUNTER', if_true: files= ('sse-counter.c')) softmmu_ss.add(when: 'CONFIG_SSE_TIMER', if_true: files('sse-timer.c')) softmmu_ss.add(when: 'CONFIG_STM32F2XX_TIMER', if_true: files('stm32f2xx_t= imer.c')) softmmu_ss.add(when: 'CONFIG_XILINX', if_true: files('xilinx_timer.c')) +specific_ss.add(when: 'CONFIG_IBEX', if_true: files('ibex_timer.c')) =20 specific_ss.add(when: 'CONFIG_AVR_TIMER16', if_true: files('avr_timer16.c'= )) --=20 2.31.1 From nobody Tue May 7 04:13:01 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; 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IronPort-SDR: 32LuroljRxZ4RKhIJTYwF8fIgk+ftS0mmGOKpKAHhtAOk90K8cALtKc5jAfzxVPb4XuP8sH9YK k5ahEgDMvw7/TU5EOoCarLngwYzCyHIDhAmOLt7WmB9wIRGeLzyzG5KthNCrvhDWmxWWZVkHQN CmXEmcln9HKw778LYtXv6e9O0Q09ncR40fFft2DHwRhQUTdpsE6PQlWkLjwrq8e4h/9o7JTwxM WW68/qw3vO0KeakC7shipa4uJn5T50u0I/Hb4mZM9CvS56iiKDE3zHFzCyN3r2HNKpCdJdYSrC dMI= X-IronPort-AV: E=Sophos;i="5.83,259,1616428800"; d="scan'208";a="175980866" IronPort-SDR: QWhWnVf5BPSQClHE41rQ1ZRmwL1RQS17yEA3znSDgWgfaCF/GsztEts3X+FCDTLuNe0PYoxG51 cOjVIruZBYLy6d84AUVzXHUKqxJa8xzQfmVcP6Z7cSdu1gyICc3cf1fo6fs35/ay0pU+nhC7z9 VIUj52K8iHEo17trP/H/Vbc80YQcFN9AKFu5GnySiwQtzXwy54zBNFW0Da9cYXEA7KfFzdBvvx G+E5ErzpgiBCm3tWfHKbU81zDKnP4+XPVb9I4adUe1i6Ood8C3BwX2i/GH7JxlfjHxn5qa4ewQ GRPz8Y4GBhuFj+k+p2fWqnKW IronPort-SDR: kgW75y2gBwWLsnIc45LXD9Qp3WbZqCGm8WgquTWC7rnQ2LlLfCqpAzs2ELhrtcnOAtX8sgVnnD urOvprI6HaaPIgno5/WsFyAZdAHT62Q9HMc37yx3BS5kx9727aA+q0wx/EWF7+9TNkZ2jVlp2M 9tXUaquOuMkBFejiqKJsx3Bzhin2nNs1Rb8d1rkhV+NDuXwdb9wwMlivHii3aD+wOXv2Pf7Zow x6s4Fq4RtURml3fw4bhsJNCSCLVcZs0XI+ZCtcdmtxV6Y+c3BGX8JtJjOacH4wD4d/GxuEvlq7 /eU= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 3/3] hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer Date: Wed, 9 Jun 2021 09:49:17 +1000 Message-Id: <0f539904158bfd88ac0aa5d604d07df41ce8be60.1623196022.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.141; envelope-from=prvs=7863c9c60=alistair.francis@wdc.com; helo=esa3.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Connect the Ibex timer to the OpenTitan machine. The timer can trigger the RISC-V MIE interrupt as well as a custom device interrupt. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng --- include/hw/riscv/opentitan.h | 5 ++++- hw/riscv/opentitan.c | 14 +++++++++++--- 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h index aab9bc9245..86cceef698 100644 --- a/include/hw/riscv/opentitan.h +++ b/include/hw/riscv/opentitan.h @@ -22,6 +22,7 @@ #include "hw/riscv/riscv_hart.h" #include "hw/intc/ibex_plic.h" #include "hw/char/ibex_uart.h" +#include "hw/timer/ibex_timer.h" #include "qom/object.h" =20 #define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc" @@ -35,6 +36,7 @@ struct LowRISCIbexSoCState { RISCVHartArrayState cpus; IbexPlicState plic; IbexUartState uart; + IbexTimerState timer; =20 MemoryRegion flash_mem; MemoryRegion rom; @@ -57,7 +59,7 @@ enum { IBEX_DEV_SPI, IBEX_DEV_I2C, IBEX_DEV_PATTGEN, - IBEX_DEV_RV_TIMER, + IBEX_DEV_TIMER, IBEX_DEV_SENSOR_CTRL, IBEX_DEV_OTP_CTRL, IBEX_DEV_PWRMGR, @@ -82,6 +84,7 @@ enum { }; =20 enum { + IBEX_TIMER_TIMEREXPIRED0_0 =3D 125, IBEX_UART0_RX_PARITY_ERR_IRQ =3D 8, IBEX_UART0_RX_TIMEOUT_IRQ =3D 7, IBEX_UART0_RX_BREAK_ERR_IRQ =3D 6, diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index 7545dcda9c..c5a7e3bacb 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -36,7 +36,7 @@ static const MemMapEntry ibex_memmap[] =3D { [IBEX_DEV_SPI] =3D { 0x40050000, 0x1000 }, [IBEX_DEV_I2C] =3D { 0x40080000, 0x1000 }, [IBEX_DEV_PATTGEN] =3D { 0x400e0000, 0x1000 }, - [IBEX_DEV_RV_TIMER] =3D { 0x40100000, 0x1000 }, + [IBEX_DEV_TIMER] =3D { 0x40100000, 0x1000 }, [IBEX_DEV_SENSOR_CTRL] =3D { 0x40110000, 0x1000 }, [IBEX_DEV_OTP_CTRL] =3D { 0x40130000, 0x4000 }, [IBEX_DEV_PWRMGR] =3D { 0x40400000, 0x1000 }, @@ -106,6 +106,8 @@ static void lowrisc_ibex_soc_init(Object *obj) object_initialize_child(obj, "plic", &s->plic, TYPE_IBEX_PLIC); =20 object_initialize_child(obj, "uart", &s->uart, TYPE_IBEX_UART); + + object_initialize_child(obj, "timer", &s->timer, TYPE_IBEX_TIMER); } =20 static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) @@ -159,6 +161,14 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_= soc, Error **errp) 3, qdev_get_gpio_in(DEVICE(&s->plic), IBEX_UART0_RX_OVERFLOW_IRQ)); =20 + if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, memmap[IBEX_DEV_TIMER].b= ase); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), + 0, qdev_get_gpio_in(DEVICE(&s->plic), + IBEX_TIMER_TIMEREXPIRED0_0)); + create_unimplemented_device("riscv.lowrisc.ibex.gpio", memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size); create_unimplemented_device("riscv.lowrisc.ibex.spi", @@ -167,8 +177,6 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_s= oc, Error **errp) memmap[IBEX_DEV_I2C].base, memmap[IBEX_DEV_I2C].size); create_unimplemented_device("riscv.lowrisc.ibex.pattgen", memmap[IBEX_DEV_PATTGEN].base, memmap[IBEX_DEV_PATTGEN].size); - create_unimplemented_device("riscv.lowrisc.ibex.rv_timer", - memmap[IBEX_DEV_RV_TIMER].base, memmap[IBEX_DEV_RV_TIMER].size); create_unimplemented_device("riscv.lowrisc.ibex.sensor_ctrl", memmap[IBEX_DEV_SENSOR_CTRL].base, memmap[IBEX_DEV_SENSOR_CTRL].si= ze); create_unimplemented_device("riscv.lowrisc.ibex.otp_ctrl", --=20 2.31.1