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[PATCH] Fix incorrect register name in RISC-V disassembler for fmv,fabs,fneg instructions

Mikhail Tyutin posted 1 patch 1 year, 1 month ago 
disas/riscv.c | 19 ++++++++++---------
1 file changed, 10 insertions(+), 9 deletions(-)
[PATCH] Fix incorrect register name in RISC-V disassembler for fmv,fabs,fneg instructions
Posted by Mikhail Tyutin 1 year, 1 month ago 
Fix incorrect register name in RISC-V disassembler for fmv,fabs,fneg instructions

Signed-off-by: Mikhail Tyutin <m.tyutin@yadro.com>
---
  disas/riscv.c | 19 ++++++++++---------
  1 file changed, 10 insertions(+), 9 deletions(-)

diff --git a/disas/riscv.c b/disas/riscv.c
index ddda687c13..58ad3df24d 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -1014,6 +1014,7 @@ static const char rv_vreg_name_sym[32][4] = {
  #define rv_fmt_rd_offset              "O\t0,o"
  #define rv_fmt_rd_rs1_rs2             "O\t0,1,2"
  #define rv_fmt_frd_rs1                "O\t3,1"
+#define rv_fmt_frd_frs1               "O\t3,4"
  #define rv_fmt_rd_frs1                "O\t0,4"
  #define rv_fmt_rd_frs1_frs2           "O\t0,4,5"
  #define rv_fmt_frd_frs1_frs2          "O\t3,4,5"
@@ -1580,15 +1581,15 @@ const rv_opcode_data opcode_data[] = {
      { "snez", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
      { "sltz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
      { "sgtz", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
-    { "fmv.s", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
-    { "fabs.s", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
-    { "fneg.s", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
-    { "fmv.d", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
-    { "fabs.d", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
-    { "fneg.d", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
-    { "fmv.q", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
-    { "fabs.q", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
-    { "fneg.q", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+    { "fmv.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
+    { "fabs.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
+    { "fneg.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
+    { "fmv.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
+    { "fabs.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
+    { "fneg.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
+    { "fmv.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
+    { "fabs.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
+    { "fneg.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
      { "beqz", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 },
      { "bnez", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 },
      { "blez", rv_codec_sb, rv_fmt_rs2_offset, NULL, 0, 0, 0 },
-- 
2.34.1
Re: [PATCH] Fix incorrect register name in RISC-V disassembler for fmv,fabs,fneg instructions
Posted by Alistair Francis 1 year, 1 month ago 
On Tue, Feb 28, 2023 at 12:53 AM Mikhail Tyutin <m.tyutin@yadro.com> wrote:
>
> Fix incorrect register name in RISC-V disassembler for fmv,fabs,fneg instructions
>
> Signed-off-by: Mikhail Tyutin <m.tyutin@yadro.com>

It looks like this needs to be rebased. Do you mind rebasing it and
sending a v2?

Alistair

> ---
>   disas/riscv.c | 19 ++++++++++---------
>   1 file changed, 10 insertions(+), 9 deletions(-)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index ddda687c13..58ad3df24d 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -1014,6 +1014,7 @@ static const char rv_vreg_name_sym[32][4] = {
>   #define rv_fmt_rd_offset              "O\t0,o"
>   #define rv_fmt_rd_rs1_rs2             "O\t0,1,2"
>   #define rv_fmt_frd_rs1                "O\t3,1"
> +#define rv_fmt_frd_frs1               "O\t3,4"
>   #define rv_fmt_rd_frs1                "O\t0,4"
>   #define rv_fmt_rd_frs1_frs2           "O\t0,4,5"
>   #define rv_fmt_frd_frs1_frs2          "O\t3,4,5"
> @@ -1580,15 +1581,15 @@ const rv_opcode_data opcode_data[] = {
>       { "snez", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
>       { "sltz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
>       { "sgtz", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
> -    { "fmv.s", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> -    { "fabs.s", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> -    { "fneg.s", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> -    { "fmv.d", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> -    { "fabs.d", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> -    { "fneg.d", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> -    { "fmv.q", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> -    { "fabs.q", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> -    { "fneg.q", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> +    { "fmv.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
> +    { "fabs.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
> +    { "fneg.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
> +    { "fmv.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
> +    { "fabs.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
> +    { "fneg.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
> +    { "fmv.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
> +    { "fabs.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
> +    { "fneg.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
>       { "beqz", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 },
>       { "bnez", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 },
>       { "blez", rv_codec_sb, rv_fmt_rs2_offset, NULL, 0, 0, 0 },
> --
> 2.34.1
>
>
Re: [PATCH] Fix incorrect register name in RISC-V disassembler for fmv,fabs,fneg instructions
Posted by Alistair Francis 1 year, 1 month ago 
On Tue, Feb 28, 2023 at 12:53 AM Mikhail Tyutin <m.tyutin@yadro.com> wrote:
>
> Fix incorrect register name in RISC-V disassembler for fmv,fabs,fneg instructions
>
> Signed-off-by: Mikhail Tyutin <m.tyutin@yadro.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>   disas/riscv.c | 19 ++++++++++---------
>   1 file changed, 10 insertions(+), 9 deletions(-)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index ddda687c13..58ad3df24d 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -1014,6 +1014,7 @@ static const char rv_vreg_name_sym[32][4] = {
>   #define rv_fmt_rd_offset              "O\t0,o"
>   #define rv_fmt_rd_rs1_rs2             "O\t0,1,2"
>   #define rv_fmt_frd_rs1                "O\t3,1"
> +#define rv_fmt_frd_frs1               "O\t3,4"
>   #define rv_fmt_rd_frs1                "O\t0,4"
>   #define rv_fmt_rd_frs1_frs2           "O\t0,4,5"
>   #define rv_fmt_frd_frs1_frs2          "O\t3,4,5"
> @@ -1580,15 +1581,15 @@ const rv_opcode_data opcode_data[] = {
>       { "snez", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
>       { "sltz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
>       { "sgtz", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
> -    { "fmv.s", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> -    { "fabs.s", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> -    { "fneg.s", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> -    { "fmv.d", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> -    { "fabs.d", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> -    { "fneg.d", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> -    { "fmv.q", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> -    { "fabs.q", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> -    { "fneg.q", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> +    { "fmv.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
> +    { "fabs.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
> +    { "fneg.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
> +    { "fmv.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
> +    { "fabs.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
> +    { "fneg.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
> +    { "fmv.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
> +    { "fabs.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
> +    { "fneg.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
>       { "beqz", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 },
>       { "bnez", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 },
>       { "blez", rv_codec_sb, rv_fmt_rs2_offset, NULL, 0, 0, 0 },
> --
> 2.34.1
>
>

Patchew 2.1-devel-8c64711

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