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[178.140.16.138]) by smtp.gmail.com with ESMTPSA id t10sm757832lja.47.2017.07.22.15.16.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 22 Jul 2017 15:16:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=rIBS7YdoDjtW2bJ3l1aFA9YuYSMk+NiXjDEoUSvWLyE=; b=nPDUIfnp8uZMflSIXaMWM3IMUOsDM+Lk+9csoI17WOQ6DRJq8rHbTN+YH9DXU+mYQE iDiuzacX/pXIVq0x+NVY5uXm4G9K5tdqYfVcQLmarF00qU5AaIOrXBdb+1/fGU1WwdIr qQNlZ+7e0Ou91Fh0pcM6QFTo7TzeZa6mDLsYxPvqzPrfktCVlc5iDeqfI3TE6n00r8e/ 6gQaJtWDTV4P00mER/QaU4gFDrwNVca3/Pk4KHs4mTB0J9T9fNGepUqja9Q4enG7CJcp KzNxflLdBuqoiK0fSj77n9pFHVlzD54UU8+1cMt5UJYsP97W6otWBhaJl/buWbgO34Vm YYtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=rIBS7YdoDjtW2bJ3l1aFA9YuYSMk+NiXjDEoUSvWLyE=; b=cY9Bh09qWSfhkOcyviagEFAMzZ0Q/2eS2AIZoTvooMTncdtoX/c5V46RIXRyKdHz17 LHUgsJiUhU8yBAKcwEAJ/06MFoccUyoqCQ7jVGVz3gj0EJALTv4RbpckP7cIMf6AGwcN eq4781nsoagNplM+zBKkLEnuAvF22Eg1liMfzKAKO2pmrdhFUkaDRuDMszfF5hJ9CdW/ uHziCFz90zLEClMIit6WPsquMOOjl5e+CwvYtw3EiFilXWbxpith5bjqQneJhQrPb/A1 4WnMySBcoPHL25SIgut9TvhuLuz6oS4AcRZQHjorWbNIRjfi/vLnzAEO3EgxDka9n0L/ Gh0A== X-Gm-Message-State: AIVw110h3/7/AYZaciYdTLk8sNPIjv3n8S+MuQBacgDPOV1VJxR2l99L ibtvna8dmQJt1Q== X-Received: by 10.25.151.19 with SMTP id z19mr101822lfd.134.1500761762557; Sat, 22 Jul 2017 15:16:02 -0700 (PDT) From: Aleksandr Bezzubikov To: qemu-devel@nongnu.org Date: Sun, 23 Jul 2017 01:15:40 +0300 Message-Id: <1500761743-1669-4-git-send-email-zuban32s@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500761743-1669-1-git-send-email-zuban32s@gmail.com> References: <1500761743-1669-1-git-send-email-zuban32s@gmail.com> X-Spam-Score: -5.8 (-----) Subject: [SeaBIOS] [RFC PATCH v2 3/6] hw/pci: enable SHPC for PCIE-PCI bridge X-BeenThere: seabios@seabios.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SeaBIOS mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mst@redhat.com, seabios@seabios.org, kraxel@redhat.com, pbonzini@redhat.com, marcel@redhat.com, rth@twiddle.net MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: seabios-bounces@seabios.org Sender: "SeaBIOS" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Aleksandr Bezzubikov --- hw/pci-bridge/pcie_pci_bridge.c | 63 +++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 62 insertions(+), 1 deletion(-) diff --git a/hw/pci-bridge/pcie_pci_bridge.c b/hw/pci-bridge/pcie_pci_bridg= e.c index 0991a7b..38f665f 100644 --- a/hw/pci-bridge/pcie_pci_bridge.c +++ b/hw/pci-bridge/pcie_pci_bridge.c @@ -28,6 +28,7 @@ #include "hw/pci/pci_bus.h" #include "hw/pci/pci_bridge.h" #include "hw/pci/msi.h" +#include "hw/pci/shpc.h" #include "hw/pci/slotid_cap.h" =20 typedef struct PCIEPCIBridge { @@ -35,6 +36,7 @@ typedef struct PCIEPCIBridge { PCIBridge parent_obj; uint32_t flags; =20 + MemoryRegion bar; /*< public >*/ } PCIEPCIBridge; =20 @@ -44,11 +46,22 @@ typedef struct PCIEPCIBridge { =20 static void pciepci_bridge_realize(PCIDevice *d, Error **errp) { + PCIBridge *br =3D PCI_BRIDGE(d); + PCIEPCIBridge *bridge_dev =3D PCIE_PCI_BRIDGE_DEV(d); int rc, pos; Error *local_err =3D NULL; =20 pci_bridge_initfn(d, TYPE_PCI_BUS); =20 + d->config[PCI_INTERRUPT_PIN] =3D 0x1; + memory_region_init(&bridge_dev->bar, OBJECT(d), "shpc-bar", + shpc_bar_size(d)); + rc =3D shpc_init(d, &br->sec_bus, &bridge_dev->bar, 0, &local_err); + if (rc) { + error_propagate(errp, local_err); + goto error; + } + rc =3D pcie_cap_init(d, 0, PCI_EXP_TYPE_PCI_BRIDGE, 0, &local_err); if (rc < 0) { error_propagate(errp, local_err); @@ -78,6 +91,9 @@ static void pciepci_bridge_realize(PCIDevice *d, Error **= errp) goto error; } =20 + pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY | + PCI_BASE_ADDRESS_MEM_TYPE_64, &bridge_dev->bar); + return; =20 error: @@ -86,7 +102,9 @@ static void pciepci_bridge_realize(PCIDevice *d, Error *= *errp) =20 static void pciepci_bridge_exit(PCIDevice *d) { + PCIEPCIBridge *bridge_dev =3D PCIE_PCI_BRIDGE_DEV(d); pcie_cap_exit(d); + shpc_cleanup(d, &bridge_dev->bar); pci_bridge_exitfn(d); } =20 @@ -95,6 +113,7 @@ static void pciepci_bridge_reset(DeviceState *qdev) PCIDevice *d =3D PCI_DEVICE(qdev); pci_bridge_reset(qdev); msi_reset(d); + shpc_reset(d); } =20 static void pcie_pci_bridge_write_config(PCIDevice *d, @@ -102,8 +121,15 @@ static void pcie_pci_bridge_write_config(PCIDevice *d, { pci_bridge_write_config(d, address, val, len); msi_write_config(d, address, val, len); + shpc_cap_write_config(d, address, val, len); } =20 +static bool pci_device_shpc_present(void *opaque, int version_id) +{ + PCIDevice *dev =3D opaque; + + return shpc_present(dev); +} =20 static Property pcie_pci_bridge_dev_properties[] =3D { DEFINE_PROP_END_OF_LIST(), @@ -113,14 +139,43 @@ static const VMStateDescription pciepci_bridge_dev_vm= state =3D { .name =3D TYPE_PCIE_PCI_BRIDGE_DEV, .fields =3D (VMStateField[]) { VMSTATE_PCI_DEVICE(parent_obj, PCIBridge), + SHPC_VMSTATE(shpc, PCIDevice, pci_device_shpc_present), VMSTATE_END_OF_LIST() } }; =20 +static void pcie_pci_bridge_hotplug_cb(HotplugHandler *hotplug_dev, + DeviceState *dev, Error **errp) +{ + PCIDevice *pci_hotplug_dev =3D PCI_DEVICE(hotplug_dev); + + if (!shpc_present(pci_hotplug_dev)) { + error_setg(errp, "standard hotplug controller has been disabled fo= r " + "this %s", TYPE_PCIE_PCI_BRIDGE_DEV); + return; + } + shpc_device_hotplug_cb(hotplug_dev, dev, errp); +} + +static void pcie_pci_bridge_hot_unplug_request_cb(HotplugHandler *hotplug_= dev, + DeviceState *dev, + Error **errp) +{ + PCIDevice *pci_hotplug_dev =3D PCI_DEVICE(hotplug_dev); + + if (!shpc_present(pci_hotplug_dev)) { + error_setg(errp, "standard hotplug controller has been disabled fo= r " + "this %s", TYPE_PCIE_PCI_BRIDGE_DEV); + return; + } + shpc_device_hot_unplug_request_cb(hotplug_dev, dev, errp); +} + static void pciepci_bridge_class_init(ObjectClass *klass, void *data) { PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); DeviceClass *dc =3D DEVICE_CLASS(klass); + HotplugHandlerClass *hc =3D HOTPLUG_HANDLER_CLASS(klass); =20 k->is_express =3D 1; k->is_bridge =3D 1; @@ -134,13 +189,19 @@ static void pciepci_bridge_class_init(ObjectClass *kl= ass, void *data) dc->vmsd =3D &pciepci_bridge_dev_vmstate; dc->reset =3D &pciepci_bridge_reset; set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); + hc->plug =3D pcie_pci_bridge_hotplug_cb; + hc->unplug_request =3D pcie_pci_bridge_hot_unplug_request_cb; } =20 static const TypeInfo pciepci_bridge_info =3D { .name =3D TYPE_PCIE_PCI_BRIDGE_DEV, .parent =3D TYPE_PCI_BRIDGE, .instance_size =3D sizeof(PCIEPCIBridge), - .class_init =3D pciepci_bridge_class_init + .class_init =3D pciepci_bridge_class_init, + .interfaces =3D (InterfaceInfo[]) { + { TYPE_HOTPLUG_HANDLER }, + { }, + } }; =20 static void pciepci_register(void) --=20 2.7.4 _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios