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[95.84.133.8]) by smtp.gmail.com with ESMTPSA id v126sm732360lfa.21.2017.07.28.16.38.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 28 Jul 2017 16:38:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Bw3NM/OhB/t10s8w4nv7tzL1p8wu17CGVQKoWKt5CC8=; b=MjErMsHUEIJ06CvtgzM17zUaGbf3tRy6qNfxwpGVY8plMTUqjmENApYucIUWygUHnt lelGHVmgEnTfJg4pHRtO5dway5rZvEw1fqlJ6Nr1pQTE9q9qLq2H2FFNwVP0GLtigzoZ XSQ9EuB2Tdiwr0/WmplmBvDv30smwXv9PAmwojfo2bvxtwoHFeVxyssnUqDpIzEllYEF I70eJhHdj0kcLOD4vdK/fOxcDU7gNGrSWiCOMZ0tAfUq0/6pKXQFEt2EXOeBLZXRW7MC J61GiWfgJPOWE8RNNZRr0vZKBZDIuxTAdRZHgUDiEmJBRy0GV9n5x78jRoqg6+mjtMjb vZkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Bw3NM/OhB/t10s8w4nv7tzL1p8wu17CGVQKoWKt5CC8=; b=EtSYY4QuMh6j0bZWUPUEsszHTDyKMWFxQ2/VW++OJOSyIx1hu2/EFMAlOyMgCMwrSh D5b1k0w4w3M2OgiyPap2JfSEB2hHmfqDRk3xnOivRxBmMfLlxDhKHz08DijsrwRAsKgp HuqjkQDt+WXSW6/KSxKLqhQjcc6wxr3qzUJZWD3VpOfpo3ujUiqwlMrKEVrwrscpbbGO suEE49E1pQrNcvMIfGZFVnCNa9BYkBTZ68OHkTJS24GIrCDx3hRTnCI0NBEMvZZP/R/q HqFCsmtmSf9SB0xv0h03CpofTQ1xWyft0IxolUb2m7nggbCzpEzr8Tx3XlIV8RfcPwsv bK7w== X-Gm-Message-State: AIVw110jFT/iJWZ+hGVDYr6TbKy2U2WS1KuxlPCYG68eFoscEEAIpn1h ySrZy32EO867AACQzGQ= X-Received: by 10.46.83.17 with SMTP id h17mr1961116ljb.186.1501285081534; Fri, 28 Jul 2017 16:38:01 -0700 (PDT) From: Aleksandr Bezzubikov To: qemu-devel@nongnu.org Date: Sat, 29 Jul 2017 02:37:51 +0300 Message-Id: <1501285073-2215-4-git-send-email-zuban32s@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501285073-2215-1-git-send-email-zuban32s@gmail.com> References: <1501285073-2215-1-git-send-email-zuban32s@gmail.com> X-Spam-Score: -1.1 (-) Subject: [SeaBIOS] [PATCH v3 3/5] hw/pci: introduce bridge-only vendor-specific capability to provide some hints to firmware X-BeenThere: seabios@seabios.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SeaBIOS mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mst@redhat.com, seabios@seabios.org, kraxel@redhat.com, pbonzini@redhat.com, marcel@redhat.com, lersek@redhat.com, rth@twiddle.net MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: seabios-bounces@seabios.org Sender: "SeaBIOS" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" On PCI init PCI bridges may need some extra info about bus number to reserve, IO, memory and prefetchable memory limits. QEMU can provide this with a special vendor-specific PCI capability. Signed-off-by: Aleksandr Bezzubikov --- hw/pci/pci_bridge.c | 37 +++++++++++++++++++++++++++++++++++++ include/hw/pci/pci_bridge.h | 28 ++++++++++++++++++++++++++++ 2 files changed, 65 insertions(+) diff --git a/hw/pci/pci_bridge.c b/hw/pci/pci_bridge.c index 720119b..e9f12d6 100644 --- a/hw/pci/pci_bridge.c +++ b/hw/pci/pci_bridge.c @@ -408,6 +408,43 @@ void pci_bridge_map_irq(PCIBridge *br, const char* bus= _name, br->bus_name =3D bus_name; } =20 + +int pci_bridge_qemu_cap_init(PCIDevice *dev, int cap_offset, + uint8_t bus_reserve, uint32_t io_reserve, + uint16_t non_pref_reserve, uint64_t pref_res= erve, + Error **errp) +{ + size_t cap_len =3D sizeof(PCIBridgeQemuCap); + PCIBridgeQemuCap cap =3D { + .len =3D cap_len, + .type =3D REDHAT_PCI_CAP_QEMU, + .bus_res =3D bus_reserve, + .non_pref_16 =3D non_pref_reserve + }; + + if ((uint8_t)io_reserve =3D=3D io_reserve) { + cap.io_8 =3D io_reserve; + } else { + cap.io_32 =3D io_reserve; + } + if ((uint16_t)pref_reserve =3D=3D pref_reserve) { + cap.pref_32 =3D pref_reserve; + } else { + cap.pref_64 =3D pref_reserve; + } + + int offset =3D pci_add_capability(dev, PCI_CAP_ID_VNDR, + cap_offset, cap_len, errp); + if (offset < 0) { + return offset; + } + + memcpy(dev->config + offset + PCI_CAP_FLAGS, + (char *)&cap + PCI_CAP_FLAGS, + cap_len - PCI_CAP_FLAGS); + return 0; +} + static const TypeInfo pci_bridge_type_info =3D { .name =3D TYPE_PCI_BRIDGE, .parent =3D TYPE_PCI_DEVICE, diff --git a/include/hw/pci/pci_bridge.h b/include/hw/pci/pci_bridge.h index ff7cbaa..e9b7cf4 100644 --- a/include/hw/pci/pci_bridge.h +++ b/include/hw/pci/pci_bridge.h @@ -67,4 +67,32 @@ void pci_bridge_map_irq(PCIBridge *br, const char* bus_n= ame, #define PCI_BRIDGE_CTL_DISCARD_STATUS 0x400 /* Discard timer status */ #define PCI_BRIDGE_CTL_DISCARD_SERR 0x800 /* Discard timer SERR# enable */ =20 +typedef struct PCIBridgeQemuCap { + uint8_t id; /* Standard PCI capability header field */ + uint8_t next; /* Standard PCI capability header field */ + uint8_t len; /* Standard PCI vendor-specific capability header fiel= d */ + uint8_t type; /* Red Hat vendor-specific capability type. + Types are defined with REDHAT_PCI_CAP_ prefix */ + + uint16_t non_pref_16; /* Non-prefetchable memory limit */ + uint8_t bus_res; /* Minimum number of buses to reserve */ + uint8_t io_8; /* IO space limit in case of 8-bit value */ + uint32_t io_32; /* IO space limit in case of 32-bit value + This 2 values are mutually exclusive, + i.e. they can't be >0 both*/ + uint32_t pref_32; /* Prefetchable memory limit + in case of 32-bit value */ + uint64_t pref_64; /* Prefetchable memory limit + in case of 64-bit value + This 2 values are mutually exclusive (just = as + IO limit), i.e. they can't be >0 both */ +} PCIBridgeQemuCap; + +#define REDHAT_PCI_CAP_QEMU 1 + +int pci_bridge_qemu_cap_init(PCIDevice *dev, int cap_offset, + uint8_t bus_reserve, uint32_t io_reserve, + uint16_t mem_reserve, uint64_t pref_reserve, + Error **errp); + #endif /* QEMU_PCI_BRIDGE_H */ --=20 2.7.4 _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios