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[95.84.133.8]) by smtp.gmail.com with ESMTPSA id v126sm732360lfa.21.2017.07.28.16.38.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 28 Jul 2017 16:38:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=FsDtWyqa/xakCn61nt8oC6F7aIZuYYb4JbsTAXKAQdI=; b=AbWHBpxiuCciS3dQVAuYujQjs/iCj7ffaiosPs/X2nIp2VY3vQSjSmFJMnXTNzvske OK5y4NTmel615O8vm8do95lLAsKlc8ztTjmbwabREA1n6a1G6mo+X80FwD+LCCbP90Ex Xwn8rrUOlojPc3PkRK7IMZufpUrFl4Z3oJ+eSpjP0PgxVzZgcoKYQhI3xs8IzDOwLwg/ GEO0LH7WqZsZocnRNAfpo92wkJZC6lGuppK3sDjTgfJJd8Ld18HWEaVw7ThCvuGsWptn 9mmEryVsusJQdmKUYJ/yI+GLhbRkBu6Ss+lvYb5SVS4JfNNFPNn9yPCTZfMOP6NAXJBB 3DPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=FsDtWyqa/xakCn61nt8oC6F7aIZuYYb4JbsTAXKAQdI=; b=MQ0fF0RjeNc7MrFw7jwkOTp55fGI/28+CqHPbawe9anjHarrdl/EYvTOA4NHXhA8Mb /vwVlnHuY/3ETDfoGN7Rd0e6oZtM/9Yjo/pERxkcKzvo/eDATMtmafBkXyFxTkl6VA6D r4T4rz7sDHTBgfkLS6SAvf9xjB2MJg1KYXtw1Y0xKiX5SxlQDq1F4lmhDoy7RtY2ObW7 e/sH/7euEzO4yrE3P4x9P71rRqXeRlrOhMIWNqt3mW6C6ImB9cENCAuqOo7HNa0j2K67 L1hFlIFByxnw3VFnlTCItppQ0qZA8xHiLXMyOmAG1d9Vp3sCi5BV2LSWj1Gbqc82ajd+ mr8Q== X-Gm-Message-State: AIVw111ikrxP+uKIzKDtz2/Ef/c3HsQCZYb5Mw44RUhiHYN5cKN7+KbB UMVT2mqfg4YLEA== X-Received: by 10.46.84.81 with SMTP id y17mr607674ljd.133.1501285083245; Fri, 28 Jul 2017 16:38:03 -0700 (PDT) From: Aleksandr Bezzubikov To: qemu-devel@nongnu.org Date: Sat, 29 Jul 2017 02:37:52 +0300 Message-Id: <1501285073-2215-5-git-send-email-zuban32s@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501285073-2215-1-git-send-email-zuban32s@gmail.com> References: <1501285073-2215-1-git-send-email-zuban32s@gmail.com> X-Spam-Score: 2.4 (++) Subject: [SeaBIOS] [PATCH v3 4/5] hw/pci: add QEMU-specific PCI capability to Generic PCI Express Root Port X-BeenThere: seabios@seabios.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SeaBIOS mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mst@redhat.com, seabios@seabios.org, kraxel@redhat.com, Aleksandr Bezzubikov , pbonzini@redhat.com, marcel@redhat.com, lersek@redhat.com, rth@twiddle.net MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: seabios-bounces@seabios.org Sender: "SeaBIOS" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Aleksandr Bezzubikov To enable hotplugging of a newly created pcie-pci-bridge, we need to tell firmware (SeaBIOS in this case) to reserve additional buses for pcie-root-port, that allows us to hotplug pcie-pci-bridge into this root port. The number of buses to reserve is provided to the device via a corresponding property, and to the firmware via new PCI capability. The property's default value is 0 to keep default behavior unchanged. Signed-off-by: Aleksandr Bezzubikov --- hw/pci-bridge/gen_pcie_root_port.c | 23 +++++++++++++++++++++++ hw/pci-bridge/pcie_root_port.c | 2 +- include/hw/pci/pcie_port.h | 2 ++ 3 files changed, 26 insertions(+), 1 deletion(-) diff --git a/hw/pci-bridge/gen_pcie_root_port.c b/hw/pci-bridge/gen_pcie_ro= ot_port.c index cb694d6..da3caa1 100644 --- a/hw/pci-bridge/gen_pcie_root_port.c +++ b/hw/pci-bridge/gen_pcie_root_port.c @@ -16,6 +16,8 @@ #include "hw/pci/pcie_port.h" =20 #define TYPE_GEN_PCIE_ROOT_PORT "pcie-root-port" +#define GEN_PCIE_ROOT_PORT(obj) \ + OBJECT_CHECK(GenPCIERootPort, (obj), TYPE_GEN_PCIE_ROOT_PORT) =20 #define GEN_PCIE_ROOT_PORT_AER_OFFSET 0x100 #define GEN_PCIE_ROOT_PORT_MSIX_NR_VECTOR 1 @@ -26,6 +28,9 @@ typedef struct GenPCIERootPort { /*< public >*/ =20 bool migrate_msix; + + /* additional buses to reserve on firmware init */ + uint8_t bus_reserve; } GenPCIERootPort; =20 static uint8_t gen_rp_aer_vector(const PCIDevice *d) @@ -60,6 +65,21 @@ static bool gen_rp_test_migrate_msix(void *opaque, int v= ersion_id) return rp->migrate_msix; } =20 +static void gen_rp_realize(PCIDevice *d, Error **errp) +{ + rp_realize(d, errp); + PCIESlot *s =3D PCIE_SLOT(d); + GenPCIERootPort *grp =3D GEN_PCIE_ROOT_PORT(d); + + int rc =3D pci_bridge_qemu_cap_init(d, 0, grp->bus_reserve, 0, 0, 0, e= rrp); + if (rc < 0) { + pcie_chassis_del_slot(s); + pcie_cap_exit(d); + gen_rp_interrupts_uninit(d); + pci_bridge_exitfn(d); + } +} + static const VMStateDescription vmstate_rp_dev =3D { .name =3D "pcie-root-port", .version_id =3D 1, @@ -78,6 +98,7 @@ static const VMStateDescription vmstate_rp_dev =3D { =20 static Property gen_rp_props[] =3D { DEFINE_PROP_BOOL("x-migrate-msix", GenPCIERootPort, migrate_msix, true= ), + DEFINE_PROP_UINT8("bus-reserve", GenPCIERootPort, bus_reserve, 0), DEFINE_PROP_END_OF_LIST() }; =20 @@ -89,6 +110,8 @@ static void gen_rp_dev_class_init(ObjectClass *klass, vo= id *data) =20 k->vendor_id =3D PCI_VENDOR_ID_REDHAT; k->device_id =3D PCI_DEVICE_ID_REDHAT_PCIE_RP; + k->realize =3D gen_rp_realize; + dc->desc =3D "PCI Express Root Port"; dc->vmsd =3D &vmstate_rp_dev; dc->props =3D gen_rp_props; diff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c index 4d588cb..2f3bcb1 100644 --- a/hw/pci-bridge/pcie_root_port.c +++ b/hw/pci-bridge/pcie_root_port.c @@ -52,7 +52,7 @@ static void rp_reset(DeviceState *qdev) pci_bridge_disable_base_limit(d); } =20 -static void rp_realize(PCIDevice *d, Error **errp) +void rp_realize(PCIDevice *d, Error **errp) { PCIEPort *p =3D PCIE_PORT(d); PCIESlot *s =3D PCIE_SLOT(d); diff --git a/include/hw/pci/pcie_port.h b/include/hw/pci/pcie_port.h index 1333266..febd96a 100644 --- a/include/hw/pci/pcie_port.h +++ b/include/hw/pci/pcie_port.h @@ -63,6 +63,8 @@ void pcie_chassis_del_slot(PCIESlot *s); #define PCIE_ROOT_PORT_GET_CLASS(obj) \ OBJECT_GET_CLASS(PCIERootPortClass, (obj), TYPE_PCIE_ROOT_PORT) =20 +void rp_realize(PCIDevice *d, Error **errp); + typedef struct PCIERootPortClass { PCIDeviceClass parent_class; =20 --=20 2.7.4 _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios