From nobody Tue Dec 16 08:32:55 2025 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) client-ip=80.81.252.135; envelope-from=seabios-bounces@seabios.org; helo=mail.coreboot.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) smtp.mailfrom=seabios-bounces@seabios.org Return-Path: Received: from mail.coreboot.org (mail.coreboot.org [80.81.252.135]) by mx.zohomail.com with SMTPS id 1501964911148347.14979282523507; Sat, 5 Aug 2017 13:28:31 -0700 (PDT) Received: from [127.0.0.1] (helo=ra.coresystems.de) by mail.coreboot.org with esmtp (Exim 4.86_2) (envelope-from ) id 1de5du-0004G7-4n; Sat, 05 Aug 2017 22:25:50 +0200 Received: from mail-lf0-f66.google.com ([209.85.215.66]) by mail.coreboot.org with esmtps (TLSv1.2:ECDHE-RSA-AES128-GCM-SHA256:128) (Exim 4.86_2) (envelope-from ) id 1de5dh-0004Bg-HI for seabios@seabios.org; Sat, 05 Aug 2017 22:25:49 +0200 Received: by mail-lf0-f66.google.com with SMTP id x16so3070686lfb.4 for ; Sat, 05 Aug 2017 13:28:00 -0700 (PDT) Received: from localhost.localdomain (broadband-109-173-19-108.moscow.rt.ru. [109.173.19.108]) by smtp.gmail.com with ESMTPSA id e42sm1978197lji.81.2017.08.05.13.27.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 05 Aug 2017 13:27:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=PL8+xV0F7+Aeqbl11BcoYp+Li+2ISLsndy0/X6SE358=; b=i8HYhbpcbKkU2tszZC1gkPCPJTkzHWLq5LyhSyZLWcO9ABrfZfzfJpm8cNszXk+pmd PJ8G5EZ9K/1I4uZ9gj9HdWOcH/ZF48ag96ngH5BeBE7Xo+rL0dlthBr3BGmwQNd0fD5H nO9WBShu6ptlK6JiH/+koHrldFHq1eGd16PR8ZoQcyPZrShFSxymUE3TqFUvnjjzA2om TJkq1JSZQX1AytgDS+ofPD0SS5LmMR/t7v0aYmZxX1QPoZvEQWKBc6KfpBYpqrHfxa3Y Bk6bGFw80jNB5iJ/ApKNCoXlC83kij3ZQQ3xz3b34yKYf0VWHNeqrU+HztpC5O1PsQXc 1rdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=PL8+xV0F7+Aeqbl11BcoYp+Li+2ISLsndy0/X6SE358=; b=hZU6FcguqYbiVKrJev8B5IHt7yxNrfcXQzzwyMb+5lizwtrhqxo9M/45Ct43BTpXgd hN/cVXPx9ZX1cN4iDk/w2oWCLbVwD7NxeefT7lOXa9chR7TogtoWWp22idPrDbkBmvM3 bHHJJeuRjeR89Wy7WUbk7gIMAdg4QeAyFq7RSc4GBdmJcGmacoMo9OHkhGzy8wLzP6uD uXpaapI2/HYFi4XfrCL/Lf9bDYyAeX6LowaG6AhEpbdPeDqgPKmLj5wwSSAu3bddasx2 tBaSR/hfyp+yxQO+vORJoVZ73Vx52D09d5Wvo2Rm85x9i0cOKurTCFDzcTO4KgHy2dZ6 XlqA== X-Gm-Message-State: AHYfb5h/vP95ByHMi11uQ1hJHGN+8tjtbD9hKD1FiwmtizUB2k6UmUAa JA5v8tRTejz2dpsf8Ss= X-Received: by 10.46.77.77 with SMTP id a74mr2184986ljb.53.1501964878633; Sat, 05 Aug 2017 13:27:58 -0700 (PDT) From: Aleksandr Bezzubikov To: qemu-devel@nongnu.org Date: Sat, 5 Aug 2017 23:27:36 +0300 Message-Id: <1501964858-5159-4-git-send-email-zuban32s@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501964858-5159-1-git-send-email-zuban32s@gmail.com> References: <1501964858-5159-1-git-send-email-zuban32s@gmail.com> X-Spam-Score: -2.6 (--) Subject: [SeaBIOS] [PATCH v4 3/5] hw/pci: introduce bridge-only vendor-specific capability to provide some hints to firmware X-BeenThere: seabios@seabios.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SeaBIOS mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mst@redhat.com, seabios@seabios.org, kraxel@redhat.com, pbonzini@redhat.com, marcel@redhat.com, lersek@redhat.com, rth@twiddle.net MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: seabios-bounces@seabios.org Sender: "SeaBIOS" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" On PCI init PCI bridges may need some extra info about bus number, IO, memory and prefetchable memory to reserve. QEMU can provide this with a special vendor-specific PCI capability. Signed-off-by: Aleksandr Bezzubikov --- hw/pci/pci_bridge.c | 29 +++++++++++++++++++++++++++++ include/hw/pci/pci_bridge.h | 21 +++++++++++++++++++++ 2 files changed, 50 insertions(+) diff --git a/hw/pci/pci_bridge.c b/hw/pci/pci_bridge.c index 720119b..889950d 100644 --- a/hw/pci/pci_bridge.c +++ b/hw/pci/pci_bridge.c @@ -408,6 +408,35 @@ void pci_bridge_map_irq(PCIBridge *br, const char* bus= _name, br->bus_name =3D bus_name; } =20 + +int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset, + uint32_t bus_reserve, uint64_t io_reserve, + uint64_t non_pref_mem_reserve, + uint64_t pref_mem_reserve, + Error **errp) +{ + size_t cap_len =3D sizeof(PCIBridgeQemuCap); + PCIBridgeQemuCap cap =3D { + .len =3D cap_len, + .type =3D REDHAT_PCI_CAP_QEMU_RESERVE, + .bus_res =3D bus_reserve, + .io =3D io_reserve, + .mem =3D non_pref_mem_reserve, + .mem_pref =3D pref_mem_reserve + }; + + int offset =3D pci_add_capability(dev, PCI_CAP_ID_VNDR, + cap_offset, cap_len, errp); + if (offset < 0) { + return offset; + } + + memcpy(dev->config + offset + PCI_CAP_FLAGS, + (char *)&cap + PCI_CAP_FLAGS, + cap_len - PCI_CAP_FLAGS); + return 0; +} + static const TypeInfo pci_bridge_type_info =3D { .name =3D TYPE_PCI_BRIDGE, .parent =3D TYPE_PCI_DEVICE, diff --git a/include/hw/pci/pci_bridge.h b/include/hw/pci/pci_bridge.h index ff7cbaa..be565f7 100644 --- a/include/hw/pci/pci_bridge.h +++ b/include/hw/pci/pci_bridge.h @@ -67,4 +67,25 @@ void pci_bridge_map_irq(PCIBridge *br, const char* bus_n= ame, #define PCI_BRIDGE_CTL_DISCARD_STATUS 0x400 /* Discard timer status */ #define PCI_BRIDGE_CTL_DISCARD_SERR 0x800 /* Discard timer SERR# enable */ =20 +typedef struct PCIBridgeQemuCap { + uint8_t id; /* Standard PCI capability header field */ + uint8_t next; /* Standard PCI capability header field */ + uint8_t len; /* Standard PCI vendor-specific capability header fiel= d */ + uint8_t type; /* Red Hat vendor-specific capability type. + Types are defined with REDHAT_PCI_CAP_ prefix */ + + uint32_t bus_res; /* Minimum number of buses to reserve */ + uint64_t io; /* IO space to reserve */ + uint64_t mem; /* Non-prefetchable memory to reserve */ + uint64_t mem_pref; /* Prefetchable memory to reserve */ +} PCIBridgeQemuCap; + +#define REDHAT_PCI_CAP_QEMU_RESERVE 1 + +int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset, + uint32_t bus_reserve, uint64_t io_reserve, + uint64_t non_pref_mem_reserve, + uint64_t pref_mem_reserve, + Error **errp); + #endif /* QEMU_PCI_BRIDGE_H */ --=20 2.7.4 _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios