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[109.173.19.108]) by smtp.gmail.com with ESMTPSA id e42sm1978197lji.81.2017.08.05.13.27.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 05 Aug 2017 13:27:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=m3SdUHPJL8WRuXpeNAb33JOqecIJfljP5LnmbJ84nEU=; b=nfe/q0TDyEOBFLYlVGHxzJc4FWfZNlrFyHb4CoShqWFjyFFzBEbgX34m+s3w0jP5gG +v3PmJPyL2ZNZpDKU9Iz1s9+785sBEKHzYDtX6HHRgaRskdxmn+RUgz3GpSEirm0jlD5 FMafDwxciXYPs+h81iwAJq8FuPvogGF0ETi8yZoJDc5yoEjMqUttT4so5LzxKvlm7R9y vCFeWuYurC14gQkPVMvipQijE/5eBkEGzlSBKTsRgRclb0S65i9MQ9CvnYA2q/8VKZo+ CriyDr5Y/s0oGL0ONgX1YdW3PNNfJ+PzutciZIiIhz/0eQzM/mZ0JvmN/ueRHdDePDSX qHcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=m3SdUHPJL8WRuXpeNAb33JOqecIJfljP5LnmbJ84nEU=; b=SnnxEdXlp5lCSiWYQW7Bzvq0Ch8u0yq62qlZo27WO/vkjAEEoCnNUdIDcaN9XvItUw 5bVOPSELrumpZhtcpJkmwtk1JcA/NmZszJDsEjpsNrp0VoU/35kYx+boy4itnIpc7E+a x+/tmhlFUahMZb3nukd06cSbrQTdO2nhTkUYs02yy6qDVGeQDirx6c+qNzdrVP2e/TYh O1RnrMvcAFHLkQPH7Gxh+svsS0v7R/8AatIIr0TPN98QcS8t1Zd6F/pxFr1TDujzlgIU NOha2bJmrlVyZIUiWgrdMlArqreFXWjLfgDIG4JdgcfYGB999eIGZ9Q27aAB4sjUd6qG 46YQ== X-Gm-Message-State: AIVw113Xwbw/nA5JwAqp2NgFvqmNfQ2VeP/98GLnHVtANHXtI989F++5 EHXFtcxKxvf3RA== X-Received: by 10.46.87.81 with SMTP id r17mr2469621ljd.188.1501964880010; Sat, 05 Aug 2017 13:28:00 -0700 (PDT) From: Aleksandr Bezzubikov To: qemu-devel@nongnu.org Date: Sat, 5 Aug 2017 23:27:37 +0300 Message-Id: <1501964858-5159-5-git-send-email-zuban32s@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501964858-5159-1-git-send-email-zuban32s@gmail.com> References: <1501964858-5159-1-git-send-email-zuban32s@gmail.com> X-Spam-Score: -3.0 (---) Subject: [SeaBIOS] [PATCH v4 4/5] hw/pci: add QEMU-specific PCI capability to the Generic PCI Express Root Port X-BeenThere: seabios@seabios.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SeaBIOS mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mst@redhat.com, seabios@seabios.org, kraxel@redhat.com, pbonzini@redhat.com, marcel@redhat.com, lersek@redhat.com, rth@twiddle.net MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: seabios-bounces@seabios.org Sender: "SeaBIOS" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" To enable hotplugging of a newly created pcie-pci-bridge, we need to tell firmware (SeaBIOS in this case) to reserve additional buses or IO/MEM/PREF space for pcie-root-port. Additional bus reservation allows us to hotplug pcie-pci-bridge into this r= oot port. The number of buses to reserve is provided to the device via a corresponding property, and to the firmware via new PCI capability. The properties' default value is -1 to keep default behavior unchanged. Signed-off-by: Aleksandr Bezzubikov Reviewed-by: Marcel Apfelbaum --- hw/pci-bridge/gen_pcie_root_port.c | 33 +++++++++++++++++++++++++++++++++ include/hw/pci/pcie_port.h | 1 + 2 files changed, 34 insertions(+) diff --git a/hw/pci-bridge/gen_pcie_root_port.c b/hw/pci-bridge/gen_pcie_ro= ot_port.c index cb694d6..ff8d04c 100644 --- a/hw/pci-bridge/gen_pcie_root_port.c +++ b/hw/pci-bridge/gen_pcie_root_port.c @@ -16,6 +16,8 @@ #include "hw/pci/pcie_port.h" =20 #define TYPE_GEN_PCIE_ROOT_PORT "pcie-root-port" +#define GEN_PCIE_ROOT_PORT(obj) \ + OBJECT_CHECK(GenPCIERootPort, (obj), TYPE_GEN_PCIE_ROOT_PORT) =20 #define GEN_PCIE_ROOT_PORT_AER_OFFSET 0x100 #define GEN_PCIE_ROOT_PORT_MSIX_NR_VECTOR 1 @@ -26,6 +28,12 @@ typedef struct GenPCIERootPort { /*< public >*/ =20 bool migrate_msix; + + /* additional buses to reserve on firmware init */ + uint32_t bus_reserve; + uint64_t io_reserve; + uint64_t mem_reserve; + uint64_t pref_reserve; } GenPCIERootPort; =20 static uint8_t gen_rp_aer_vector(const PCIDevice *d) @@ -60,6 +68,23 @@ static bool gen_rp_test_migrate_msix(void *opaque, int v= ersion_id) return rp->migrate_msix; } =20 +static void gen_rp_realize(DeviceState *dev, Error **errp) +{ + PCIDevice *d =3D PCI_DEVICE(dev); + GenPCIERootPort *grp =3D GEN_PCIE_ROOT_PORT(d); + PCIERootPortClass *rpc =3D PCIE_ROOT_PORT_GET_CLASS(d); + + rpc->parent_realize(dev, errp); + + int rc =3D pci_bridge_qemu_reserve_cap_init(d, 0, grp->bus_reserve, + grp->io_reserve, grp->mem_reserve, grp->pref_reserve, errp); + + if (rc < 0) { + rpc->parent_class.exit(d); + return; + } +} + static const VMStateDescription vmstate_rp_dev =3D { .name =3D "pcie-root-port", .version_id =3D 1, @@ -78,6 +103,10 @@ static const VMStateDescription vmstate_rp_dev =3D { =20 static Property gen_rp_props[] =3D { DEFINE_PROP_BOOL("x-migrate-msix", GenPCIERootPort, migrate_msix, true= ), + DEFINE_PROP_UINT32("bus-reserve", GenPCIERootPort, bus_reserve, -1), + DEFINE_PROP_UINT64("io-reserve", GenPCIERootPort, io_reserve, -1), + DEFINE_PROP_UINT64("mem-reserve", GenPCIERootPort, mem_reserve, -1), + DEFINE_PROP_UINT64("pref-reserve", GenPCIERootPort, pref_reserve, -1), DEFINE_PROP_END_OF_LIST() }; =20 @@ -92,6 +121,10 @@ static void gen_rp_dev_class_init(ObjectClass *klass, v= oid *data) dc->desc =3D "PCI Express Root Port"; dc->vmsd =3D &vmstate_rp_dev; dc->props =3D gen_rp_props; + + rpc->parent_realize =3D dc->realize; + dc->realize =3D gen_rp_realize; + rpc->aer_vector =3D gen_rp_aer_vector; rpc->interrupts_init =3D gen_rp_interrupts_init; rpc->interrupts_uninit =3D gen_rp_interrupts_uninit; diff --git a/include/hw/pci/pcie_port.h b/include/hw/pci/pcie_port.h index 1333266..0736014 100644 --- a/include/hw/pci/pcie_port.h +++ b/include/hw/pci/pcie_port.h @@ -65,6 +65,7 @@ void pcie_chassis_del_slot(PCIESlot *s); =20 typedef struct PCIERootPortClass { PCIDeviceClass parent_class; + DeviceRealize parent_realize; =20 uint8_t (*aer_vector)(const PCIDevice *dev); int (*interrupts_init)(PCIDevice *dev, Error **errp); --=20 2.7.4 _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios