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[109.173.19.108]) by smtp.gmail.com with ESMTPSA id 79sm1952439ljf.8.2017.08.05.13.30.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 05 Aug 2017 13:30:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4mMVWnBPq5mOMACHoyRiBI8DfjN/qdoD551A0y8uexo=; b=aMxG6YsXpn6ioOFKsBiOu2W2rrJiAnhKMMfklnrXudDintRlfubngRxMTK5WCK78Re hYPPqAxGkmeUyWtXspyNWUw4dIwePYYjYO/w8MSvD+wRFbPpY20j47vcj+a/y6v300rw fBzdxrtRxyqUnZrUA0v9QDM9qM3PgWqXbgS5qADplryMgajAJ5zmxawznc+akJJp7nyN 4SqWlI1DiXLqXqVUXhEa3OF/GxLrmLB5nNVRX5h+d+igd5EYq/76jPHlj7c/0ydTrsm7 StnhLbDkHIuj6x4tkWlMpz1gJWw1PKXSBe5T6E1BJJSMUvlLuJUPTrNX0EhKYBqaoQt3 mOUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4mMVWnBPq5mOMACHoyRiBI8DfjN/qdoD551A0y8uexo=; b=taOcGppD2qxNghBUYvOitVHB7RSKgGY0IsBZZmDptqRoAks3+9psXFCvsH4p3NT/xW JsX0HxT5Wsg39zjkXDXcG5o9vLwJkYVG93ojO0mlcaWjBFSiCVwwTk5Um7Mn0pGSXLX5 rmwdhxJA+qwi9rwW06Oc5I97fMPStblDa6FdxqdEGHQSOmnqH3c3pBvL3pIi0xTQbdJp u+MSWScd7j3LTMrTpZI7Cx03ClpdaOhDsg/TC2HDhohITjJLuL4uXQUyloOAOwFXwd8F zuKGHtDvjOHqw1cvvwBSzlm3oiJYS7QFx56Mk8ECSoQhfnlq8yFzcSwNWjtYZ0h8yt9U uP4w== X-Gm-Message-State: AHYfb5iQyckM+Yezy1jcp4BrwAxR5zW+qwWMROzU/7XKsdokP1lYqM6X 8jnXJvdrQ82zdyrgaNw= X-Received: by 10.46.14.9 with SMTP id 9mr2224984ljo.26.1501965006734; Sat, 05 Aug 2017 13:30:06 -0700 (PDT) From: Aleksandr Bezzubikov To: seabios@seabios.org Date: Sat, 5 Aug 2017 23:29:53 +0300 Message-Id: <1501964994-5257-3-git-send-email-zuban32s@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501964994-5257-1-git-send-email-zuban32s@gmail.com> References: <1501964994-5257-1-git-send-email-zuban32s@gmail.com> X-Spam-Score: -2.6 (--) Subject: [SeaBIOS] [PATCH v4 2/3] pci: add QEMU-specific PCI capability structure X-BeenThere: seabios@seabios.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SeaBIOS mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mst@redhat.com, qemu-devel@nongnu.org, kraxel@redhat.com, marcel@redhat.com, lersek@redhat.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: seabios-bounces@seabios.org Sender: "SeaBIOS" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" On PCI init PCI bridge devices may need some extra info about bus number to reserve, IO, memory and prefetchable memory limits. QEMU can provide this with special vendor-specific PCI capability. This capability is intended to be used only for Red Hat PCI bridges, i.e. QEMU cooperation. Signed-off-by: Aleksandr Bezzubikov --- src/fw/dev-pci.h | 50 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 src/fw/dev-pci.h diff --git a/src/fw/dev-pci.h b/src/fw/dev-pci.h new file mode 100644 index 0000000..2c8ddb0 --- /dev/null +++ b/src/fw/dev-pci.h @@ -0,0 +1,50 @@ +#ifndef _PCI_CAP_H +#define _PCI_CAP_H + +#include "types.h" + +/* + +QEMU-specific vendor(Red Hat)-specific capability. +It's intended to provide some hints for firmware to init PCI devices. + +Its structure is shown below: + +Header: + +u8 id; Standard PCI Capability Header field +u8 next; Standard PCI Capability Header field +u8 len; Standard PCI Capability Header field +u8 type; Red Hat vendor-specific capability type: + now only REDHAT_CAP_TYP_QEMU=3D1 exists +Data: + +u32 bus_res; minimum bus number to reserve; + this is necessary for PCI Express Root Ports + to support PCIE-to-PCI bridge hotplug +u64 io; IO space to reserve +u64 mem; non-prefetchable memory space to reserve +u64 prefetchable_mem; prefetchable memory space to reserve + +If any field value in Data section is -1, +it means that such kind of reservation +is not needed and must be ignored. + +*/ + +/* Offset of vendor-specific capability type field */ +#define PCI_CAP_REDHAT_TYPE 3 + +/* List of valid Red Hat vendor-specific capability types */ +#define REDHAT_CAP_TYPE_QEMU 1 + + +/* Offsets of QEMU capability fields */ +#define QEMU_PCI_CAP_BUS_RES 4 +#define QEMU_PCI_CAP_LIMITS_OFFSET 8 +#define QEMU_PCI_CAP_IO 8 +#define QEMU_PCI_CAP_MEM 16 +#define QEMU_PCI_CAP_PREF_MEM 24 +#define QEMU_PCI_CAP_SIZE 32 + +#endif /* _PCI_CAP_H */ --=20 2.7.4 _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios