From nobody Sat May 10 07:25:35 2025 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) client-ip=80.81.252.135; envelope-from=seabios-bounces@seabios.org; helo=mail.coreboot.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) smtp.mailfrom=seabios-bounces@seabios.org Return-Path: Received: from mail.coreboot.org (mail.coreboot.org [80.81.252.135]) by mx.zohomail.com with SMTPS id 1502407330126745.8226845326808; Thu, 10 Aug 2017 16:22:10 -0700 (PDT) Received: from [127.0.0.1] (helo=ra.coresystems.de) by mail.coreboot.org with esmtp (Exim 4.86_2) (envelope-from ) id 1dfwjb-0002em-De; Fri, 11 Aug 2017 01:19:23 +0200 Received: from mail-lf0-f66.google.com ([209.85.215.66]) by mail.coreboot.org with esmtps (TLSv1.2:ECDHE-RSA-AES128-GCM-SHA256:128) (Exim 4.86_2) (envelope-from ) id 1dfwjL-0002d9-Jt for seabios@seabios.org; Fri, 11 Aug 2017 01:19:21 +0200 Received: by mail-lf0-f66.google.com with SMTP id y15so1363060lfd.5 for ; Thu, 10 Aug 2017 16:21:38 -0700 (PDT) Received: from localhost.localdomain (broadband-109-173-19-108.moscow.rt.ru. [109.173.19.108]) by smtp.gmail.com with ESMTPSA id g84sm1399994lfl.61.2017.08.10.16.21.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 10 Aug 2017 16:21:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=hFN+yM4WCJUeicW8KR6rwDTmVoViQRFuPVsqkazL6O4=; b=NW68FMzRY12ZcvtoFb3X4HFs3axkEOtFjwiUqmJj493bzN1PzZtG//WyMd7hqB4SWW NXLQmaJK9Cimtm+HoqW9aSBp8b00KsFQ6q0jowWmW4KUsFwmnZ0a61BlRQ8YBQkYUvaY 9is40UprGgt9QFnrnyXxitkY9qkhMu9Fkjt5eX5eVcWNLo++yY2ClOGMhS5n0RyDK9Rp YvgdP8LPog+WBb6fXZiexX/69E0CVWaG9foCHWWPx6ZTzoe8FnT6PWCUGiSzbXPmRMK0 yNknPVdIn2m1lJJZ6EKgopDMws05ViKF1wjilVATpicUlTLWpcXieYdGfED5OIoWLPZF 7azg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hFN+yM4WCJUeicW8KR6rwDTmVoViQRFuPVsqkazL6O4=; b=WPWZneNb5aSegikfZtqFiQzFp9pK2JgpIB1mMSLedyfRwDmc4FU22yaqFK0pIMtC97 qEnRD23Ypb7xC2/mWWctHNGPab+HbJnbLO8zKVGiglR0FxMAeZV1OVpmEtts95YmKptw YSz2wHgXISqpKzwb6oZ15VtIvimFlvCmbxerkjdEynpbuVZv+WcKOvdGGUf4hosMXSX6 7bR3ddv5CeSq8CPNLPQz5KA4095CqQQpzo9gXlgKgGVCdSlUNSrVp35+J6lginelRYYM pcxv6XzbOY+GH7C11iTLp/zRTxJ8/LXQu0049kBi/rvrMiEKpKrFDgl/8sQe9GXcLKmA M6dA== X-Gm-Message-State: AHYfb5gdtj88xIEfq+E1NtbTK15I+UjIHhlcSoZhkpwTEmari2r6dKAR piOrrBc1wsTWx5mI X-Received: by 10.25.83.139 with SMTP id h11mr4104273lfl.166.1502407296806; Thu, 10 Aug 2017 16:21:36 -0700 (PDT) From: Aleksandr Bezzubikov To: seabios@seabios.org Date: Fri, 11 Aug 2017 02:21:27 +0300 Message-Id: <1502407288-22226-3-git-send-email-zuban32s@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1502407288-22226-1-git-send-email-zuban32s@gmail.com> References: <1502407288-22226-1-git-send-email-zuban32s@gmail.com> X-Spam-Score: -7.0 (-------) Subject: [SeaBIOS] [PATCH v5 2/3] pci: add QEMU-specific PCI capability structure X-BeenThere: seabios@seabios.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SeaBIOS mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mst@redhat.com, qemu-devel@nongnu.org, kraxel@redhat.com, marcel@redhat.com, lersek@redhat.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: seabios-bounces@seabios.org Sender: "SeaBIOS" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" On PCI init PCI bridge devices may need some extra info about bus number to reserve, IO, memory and prefetchable memory limits. QEMU can provide this with special vendor-specific PCI capability. This capability is intended to be used only for Red Hat PCI bridges, i.e. QEMU cooperation. Signed-off-by: Aleksandr Bezzubikov --- src/fw/dev-pci.h | 52 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 src/fw/dev-pci.h diff --git a/src/fw/dev-pci.h b/src/fw/dev-pci.h new file mode 100644 index 0000000..cf16b2e --- /dev/null +++ b/src/fw/dev-pci.h @@ -0,0 +1,52 @@ +#ifndef _PCI_CAP_H +#define _PCI_CAP_H + +#include "types.h" + +/* + * + * QEMU-specific vendor(Red Hat)-specific capability. + * It's intended to provide some hints for firmware to init PCI devices. + * + * Its structure is shown below: + * + * Header: + * + * u8 id; Standard PCI Capability Header field + * u8 next; Standard PCI Capability Header field + * u8 len; Standard PCI Capability Header field + * u8 type; Red Hat vendor-specific capability type + * Data: + * + * u32 bus_res; minimum bus number to reserve; + * this is necessary for PCI Express Root Ports + * to support PCI bridges hotplug + * u64 io; IO space to reserve + * u32 mem; non-prefetchable memory to reserve + * + * this two fields are mutually exclusive: + * u32 prefetchable_mem_32; prefetchable memory to reserve (32-bit MMI= O) + * u64 prefetchable_mem_64; prefetchable memory to reserve (64-bit MMI= O) + * + * + * If any field value in Data section is 0xFF...F, + * it means that such kind of reservation is not needed and must be ignore= d. + * +*/ + +/* Offset of vendor-specific capability type field */ +#define PCI_CAP_REDHAT_TYPE_OFFSET 3 + +/* List of valid Red Hat vendor-specific capability types */ +#define REDHAT_CAP_RESOURCE_RESERVE 1 + + +/* Offsets of RESOURCE_RESERVE capability fields */ +#define RES_RESERVE_BUS_RES 4 +#define RES_RESERVE_IO 8 +#define RES_RESERVE_MEM 16 +#define RES_RESERVE_PREF_MEM_32 20 +#define RES_RESERVE_PREF_MEM_64 24 +#define RES_RESERVE_CAP_SIZE 32 + +#endif /* _PCI_CAP_H */ --=20 2.7.4 _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios