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[109.173.19.108]) by smtp.gmail.com with ESMTPSA id g84sm1399994lfl.61.2017.08.10.16.21.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 10 Aug 2017 16:21:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=C2aBwA9DMS/2WUY/ntIWXtEZqhvr8HlndlpZfwj8T40=; b=eNb+sV4zmaaf4/GWaOnawVMiI62MhChEooLFWJ/e8l7FtOidmcvnh6hgKCHGU6WtzT ZHbzXm5/seOxMYOevYU67N+Bz553T0OuMteVePY/EGieoz7d7RW+Fs1dG9/SnyeLlj0y DnCDUTdZdPX08irNmivvJ8ct5v5QHSToLQem4RrrxR/NHaPBaiw8oiSGEbjHpx0mqWpv HF5wB6bULsQ11P1qPBEyYsPhmYRvaeDwkV4bc5DtkQ+d+USQUWb9lHsi55YVYJiRzVU0 6vag1RkQTSvfdla5kWwtGu0azu+aLEWRt3GD9s9mA26g6JTlgFvsWKpmcBBbKaUT2/Ie n7/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=C2aBwA9DMS/2WUY/ntIWXtEZqhvr8HlndlpZfwj8T40=; b=qYYKXJRLC2aT/DxNJcXz8EunTY0cmVTfGuGGOhuqhkuJ0Na0n1i7jELP+qtgZAwJ2B j+TxGuLU0gklo97Hg2pEiXJjEeky4RCD7NVx6bq3GIUHjFhUYMLcvAd1LbuH0KzCWJiI UGPHcLNwtMmqXGd9qT+k18jpIExVSSVZJRpOLM8IFXS1zyS+g9mak6cuEtmpGMpPYdym c4CjKjmuzkl8a7kj/o8H/PE3N5ZrWDIHdWKc6N9ue6He1AFfHpoFyMWmDzNlv4YpO8/D 08Tp67cxAY+ndNGL/Twbj/0AAROkA80DP2amteH1oRJvCPY2KTYy6y+Mukk2ytztifmH hzxQ== X-Gm-Message-State: AHYfb5gXpWR9H50YWidZ3QV87iyq8UFOUQCpmjKK7xxJbYkOudxW7Ecf Axz8uINbVkj5Hu8V X-Received: by 10.25.27.20 with SMTP id b20mr4596545lfb.131.1502407304873; Thu, 10 Aug 2017 16:21:44 -0700 (PDT) From: Aleksandr Bezzubikov To: seabios@seabios.org Date: Fri, 11 Aug 2017 02:21:28 +0300 Message-Id: <1502407288-22226-4-git-send-email-zuban32s@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1502407288-22226-1-git-send-email-zuban32s@gmail.com> References: <1502407288-22226-1-git-send-email-zuban32s@gmail.com> X-Spam-Score: -4.5 (----) Subject: [SeaBIOS] [PATCH v5 3/3] pci: enable RedHat PCI bridges to reserve additional resource on PCI init X-BeenThere: seabios@seabios.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SeaBIOS mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mst@redhat.com, qemu-devel@nongnu.org, kraxel@redhat.com, marcel@redhat.com, lersek@redhat.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: seabios-bounces@seabios.org Sender: "SeaBIOS" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" In case of Red Hat Generic PCIE Root Port reserve additional buses and/or IO/MEM/PREF space, which values are provided in a vendor-specific ca= pability. Signed-off-by: Aleksandr Bezzubikov --- src/fw/dev-pci.h | 2 +- src/fw/pciinit.c | 125 +++++++++++++++++++++++++++++++++++++++++++++++++--= ---- src/hw/pci_ids.h | 3 ++ 3 files changed, 116 insertions(+), 14 deletions(-) diff --git a/src/fw/dev-pci.h b/src/fw/dev-pci.h index cf16b2e..99ccc12 100644 --- a/src/fw/dev-pci.h +++ b/src/fw/dev-pci.h @@ -38,7 +38,7 @@ #define PCI_CAP_REDHAT_TYPE_OFFSET 3 =20 /* List of valid Red Hat vendor-specific capability types */ -#define REDHAT_CAP_RESOURCE_RESERVE 1 +#define REDHAT_CAP_RESOURCE_RESERVE 1 =20 =20 /* Offsets of RESOURCE_RESERVE capability fields */ diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c index 864954f..d9aef56 100644 --- a/src/fw/pciinit.c +++ b/src/fw/pciinit.c @@ -15,6 +15,7 @@ #include "hw/pcidevice.h" // pci_probe_devices #include "hw/pci_ids.h" // PCI_VENDOR_ID_INTEL #include "hw/pci_regs.h" // PCI_COMMAND +#include "fw/dev-pci.h" // REDHAT_CAP_RESOURCE_RESERVE #include "list.h" // struct hlist_node #include "malloc.h" // free #include "output.h" // dprintf @@ -522,6 +523,32 @@ static void pci_bios_init_platform(void) } } =20 +static u8 pci_find_resource_reserve_capability(u16 bdf) +{ + if (pci_config_readw(bdf, PCI_VENDOR_ID) =3D=3D PCI_VENDOR_ID_REDHAT && + pci_config_readw(bdf, PCI_DEVICE_ID) =3D=3D + PCI_DEVICE_ID_REDHAT_ROOT_PORT) { + u8 cap =3D 0; + do { + cap =3D pci_find_capability(bdf, PCI_CAP_ID_VNDR, cap); + } while (cap && + pci_config_readb(bdf, cap + PCI_CAP_REDHAT_TYPE_OFFSET) != =3D + REDHAT_CAP_RESOURCE_RESERVE); + if (cap) { + u8 cap_len =3D pci_config_readb(bdf, cap + PCI_CAP_FLAGS); + if (cap_len < RES_RESERVE_CAP_SIZE) { + dprintf(1, "PCI: QEMU resource reserve cap length %d is in= valid\n", + cap_len); + } + } else { + dprintf(1, "PCI: invalid QEMU resource reserve cap offset\n"); + } + return cap; + } else { + dprintf(1, "PCI: QEMU resource reserve cap not found\n"); + return 0; + } +} =20 /**************************************************************** * Bus initialization @@ -578,9 +605,28 @@ pci_bios_init_bus_rec(int bus, u8 *pci_bus) pci_bios_init_bus_rec(secbus, pci_bus); =20 if (subbus !=3D *pci_bus) { + u8 res_bus =3D 0; + u8 cap =3D pci_find_resource_reserve_capability(bdf); + + if (cap) { + u32 tmp_res_bus =3D pci_config_readl(bdf, + cap + RES_RESERVE_BUS_RES); + if (tmp_res_bus !=3D (u32)-1) { + res_bus =3D tmp_res_bus & 0xFF; + if ((u8)(res_bus + secbus) < secbus || + (u8)(res_bus + secbus) < res_bus) { + dprintf(1, "PCI: bus_reserve value %d is invalid\n= ", + res_bus); + res_bus =3D 0; + } + } + res_bus =3D (*pci_bus > secbus + res_bus) ? *pci_bus + : secbus + res_bus; + } dprintf(1, "PCI: subordinate bus =3D 0x%x -> 0x%x\n", - subbus, *pci_bus); - subbus =3D *pci_bus; + subbus, res_bus); + subbus =3D res_bus; + *pci_bus =3D res_bus; } else { dprintf(1, "PCI: subordinate bus =3D 0x%x\n", subbus); } @@ -844,22 +890,74 @@ static int pci_bios_check_devices(struct pci_bus *bus= ses) */ parent =3D &busses[0]; int type; - u8 pcie_cap =3D pci_find_capability(s->bus_dev->bdf, PCI_CAP_ID_EX= P, 0); + u16 bdf =3D s->bus_dev->bdf; + u8 pcie_cap =3D pci_find_capability(bdf, PCI_CAP_ID_EXP, 0); + u8 qemu_cap =3D pci_find_resource_reserve_capability(bdf); + int hotplug_support =3D pci_bus_hotplug_support(s, pcie_cap); for (type =3D 0; type < PCI_REGION_TYPE_COUNT; type++) { u64 align =3D (type =3D=3D PCI_REGION_TYPE_IO) ? - PCI_BRIDGE_IO_MIN : PCI_BRIDGE_MEM_MIN; + PCI_BRIDGE_IO_MIN : PCI_BRIDGE_MEM_MIN; if (!pci_bridge_has_region(s->bus_dev, type)) continue; - if (pci_region_align(&s->r[type]) > align) - align =3D pci_region_align(&s->r[type]); - u64 sum =3D pci_region_sum(&s->r[type]); - int resource_optional =3D pcie_cap && (type =3D=3D PCI_REGION_= TYPE_IO); - if (!sum && hotplug_support && !resource_optional) - sum =3D align; /* reserve min size for hot-plug */ - u64 size =3D ALIGN(sum, align); - int is64 =3D pci_bios_bridge_region_is64(&s->r[type], - s->bus_dev, type); + u64 size; + int is64; + int qemu_cap_used =3D 0; + if (qemu_cap) { + u32 tmp_size; + u64 tmp_size_64; + switch(type) { + case PCI_REGION_TYPE_IO: + tmp_size_64 =3D (pci_config_readl(bdf, qemu_cap + RES_= RESERVE_IO) | + (u64)pci_config_readl(bdf, qemu_cap + RES_RESE= RVE_IO + 4) << 32); + if (tmp_size_64 !=3D (u64)-1) { + size =3D tmp_size_64; + is64 =3D 0; + qemu_cap_used =3D 1; + } + break; + case PCI_REGION_TYPE_MEM: + tmp_size =3D pci_config_readl(bdf, qemu_cap + RES_RESE= RVE_MEM); + if (tmp_size !=3D (u32)-1) { + size =3D tmp_size; + is64 =3D 0; + qemu_cap_used =3D 1; + } + break; + case PCI_REGION_TYPE_PREFMEM: + tmp_size =3D pci_config_readl(bdf, qemu_cap + RES_RESE= RVE_PREF_MEM_32); + tmp_size_64 =3D (pci_config_readl(bdf, qemu_cap + RES_= RESERVE_PREF_MEM_64) | + (u64)pci_config_readl(bdf, qemu_cap + RES_RESE= RVE_PREF_MEM_64 + 4) << 32); + if (tmp_size !=3D (u32)-1 && tmp_size_64 =3D=3D (u64)-= 1) { + size =3D tmp_size; + is64 =3D 0; + qemu_cap_used =3D 1; + } else if (tmp_size =3D=3D (u32)-1 && tmp_size_64 !=3D= (u64)-1) { + size =3D tmp_size_64; + is64 =3D 1; + qemu_cap_used =3D 1; + } else if (tmp_size !=3D (u32)-1 && tmp_size_64 !=3D (= u64)-1) { + dprintf(1, "PCI: resource reserve cap PREF32 and P= REF64" + " conflict\n"); + } + break; + default: + break; + } + } + if (!qemu_cap_used) { + if (pci_region_align(&s->r[type]) > align) + align =3D pci_region_align(&s->r[type]); + u64 sum =3D pci_region_sum(&s->r[type]); + int resource_optional =3D pcie_cap && (type =3D=3D PCI_REG= ION_TYPE_IO); + if (!sum && hotplug_support && !resource_optional) + sum =3D align; /* reserve min size for hot-plug */ + size =3D ALIGN(sum, align); + is64 =3D pci_bios_bridge_region_is64(&s->r[type], + s->bus_dev, type); + } else { + dprintf(1, "PCI: resource reserve cap used\n"); + } // entry->bar is -1 if the entry represents a bridge region struct pci_region_entry *entry =3D pci_region_create_entry( parent, s->bus_dev, -1, size, align, type, is64); @@ -951,6 +1049,7 @@ pci_region_map_one_entry(struct pci_region_entry *entr= y, u64 addr) =20 u16 bdf =3D entry->dev->bdf; u64 limit =3D addr + entry->size - 1; + if (entry->type =3D=3D PCI_REGION_TYPE_IO) { pci_config_writeb(bdf, PCI_IO_BASE, addr >> PCI_IO_SHIFT); pci_config_writew(bdf, PCI_IO_BASE_UPPER16, 0); diff --git a/src/hw/pci_ids.h b/src/hw/pci_ids.h index 4ac73b4..38fa2ca 100644 --- a/src/hw/pci_ids.h +++ b/src/hw/pci_ids.h @@ -2263,6 +2263,9 @@ #define PCI_DEVICE_ID_KORENIX_JETCARDF0 0x1600 #define PCI_DEVICE_ID_KORENIX_JETCARDF1 0x16ff =20 +#define PCI_VENDOR_ID_REDHAT 0x1b36 +#define PCI_DEVICE_ID_REDHAT_ROOT_PORT 0x000C + #define PCI_VENDOR_ID_TEKRAM 0x1de1 #define PCI_DEVICE_ID_TEKRAM_DC290 0xdc29 =20 --=20 2.7.4 _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios