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[109.173.19.108]) by smtp.gmail.com with ESMTPSA id c64sm1411547lfc.4.2017.08.10.16.31.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 10 Aug 2017 16:31:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=B+JDj4ugisiiik8NKv5iZtaF40rXEJDE/MswXZ1qp0I=; b=MxVL006ATUDfpeNh3nn9MR2eBhhFRz16PnEeELxddW2bxZKEZi8rak7LNpAJQcdIrI 5Mas9SQFdM/seBxUluxrRbWDV4gSJhrEtrs+aoeSuX07LEtP9gYJZFz/Nt0EDu+Fjiwh jj4UEB+AbxDGOyZnpZjXXKh+PiqPp9wDhIctNUa83uPVZZ5FN1bgomg/U9Kq0S/NoY2I BoAUSfmPXP183sUMc6Hps1xfjS9e8sH0McOnauONRU+yVfpfavpqK072up3wL/Ln9/vI EtOosL+jhxjjTuT0vc0abVQnvkP1xJZLS1avNotPe7SVhBmRt5fgh1eAoGwgi7C+go6l yxeQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=B+JDj4ugisiiik8NKv5iZtaF40rXEJDE/MswXZ1qp0I=; b=OxSZd8+r0AM5TMHR0vIeYRl5ujVx/U7Dps7XrSdjMsqkAGMK4/0oHk2+6nGMZoW6VZ oHyWozVszsw2pvraqP+4oZCq1RCeHR/VvUcsNwz3Hn0vTI7j9s3aq3BzbCVVnSfPNzQe S2rv8r1OyQWwM+cUq+FchvspHrtjiwTgeSBC6Qjik0XMijBgHCcacF5QoUHdRb0bK8xx xMk6LbFyYLD18NZmQtZ/dLTPh2uOc/26z8EQXbqYPaLvN9xWuzfuaGCnFo4/gUV9Gs+X xsYLdlS4hKyNR8oV0SsqPYe9r+cpGI5DM5c6B42dDevQqTPXV/ilQXJQQp6EvX+bw1ou OdkA== X-Gm-Message-State: AHYfb5jvHG4ADijBCL0GoZJt8TGUKk2tgtIDdtYpsX3NMeFu24ImczFL GNM283jAZvXGAA== X-Received: by 10.25.37.14 with SMTP id l14mr5319435lfl.177.1502407869666; Thu, 10 Aug 2017 16:31:09 -0700 (PDT) From: Aleksandr Bezzubikov To: qemu-devel@nongnu.org Date: Fri, 11 Aug 2017 02:31:01 +0300 Message-Id: <1502407863-23182-3-git-send-email-zuban32s@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1502407863-23182-1-git-send-email-zuban32s@gmail.com> References: <1502407863-23182-1-git-send-email-zuban32s@gmail.com> X-Spam-Score: -2.3 (--) Subject: [SeaBIOS] [PATCH v5 2/4] hw/pci: introduce bridge-only vendor-specific capability to provide some hints to firmware X-BeenThere: seabios@seabios.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SeaBIOS mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marcel@redhat.com, seabios@seabios.org, mst@redhat.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: seabios-bounces@seabios.org Sender: "SeaBIOS" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" On PCI init PCI bridges may need some extra info about bus number, IO, memory and prefetchable memory to reserve. QEMU can provide this with a special vendor-specific PCI capability. Signed-off-by: Aleksandr Bezzubikov Reviewed-by: Marcel Apfelbaum --- hw/pci/pci_bridge.c | 54 +++++++++++++++++++++++++++++++++++++++++= ++++ include/hw/pci/pci_bridge.h | 24 ++++++++++++++++++++ 2 files changed, 78 insertions(+) diff --git a/hw/pci/pci_bridge.c b/hw/pci/pci_bridge.c index 720119b..2495a51 100644 --- a/hw/pci/pci_bridge.c +++ b/hw/pci/pci_bridge.c @@ -408,6 +408,60 @@ void pci_bridge_map_irq(PCIBridge *br, const char* bus= _name, br->bus_name =3D bus_name; } =20 + +int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset, + uint32_t bus_reserve, uint64_t io_reserve, + uint32_t mem_non_pref_reserve, + uint32_t mem_pref_32_reserve, + uint64_t mem_pref_64_reserve, + Error **errp) +{ + if (mem_pref_32_reserve !=3D (uint32_t)-1 && + mem_pref_64_reserve !=3D (uint64_t) -1) { + error_setg(errp, + "PCI resource reserve cap: PREF32 and PREF64 conflict"); + return -EINVAL; + } + + if (bus_reserve =3D=3D (uint32_t)-1 && + io_reserve =3D=3D (uint64_t)-1 && + mem_non_pref_reserve =3D=3D (uint32_t)-1 && + mem_pref_32_reserve =3D=3D (uint32_t)-1 && + mem_pref_64_reserve =3D=3D (uint64_t)-1) { + return 0; + } + + size_t cap_len =3D sizeof(PCIBridgeQemuCap); + PCIBridgeQemuCap cap =3D { + .len =3D cap_len, + .type =3D REDHAT_PCI_CAP_RESOURCE_RESERVE, + .bus_res =3D bus_reserve, + .io =3D io_reserve, + .mem =3D mem_non_pref_reserve, + .mem_pref_32 =3D (uint32_t)-1, + .mem_pref_64 =3D (uint64_t)-1 + }; + + if (mem_pref_32_reserve !=3D (uint32_t)-1 && + mem_pref_64_reserve =3D=3D (uint64_t)-1) { + cap.mem_pref_32 =3D mem_pref_32_reserve; + } else if (mem_pref_32_reserve =3D=3D (uint32_t)-1 && + mem_pref_64_reserve !=3D (uint64_t)-1) { + cap.mem_pref_64 =3D mem_pref_64_reserve; + } + + int offset =3D pci_add_capability(dev, PCI_CAP_ID_VNDR, + cap_offset, cap_len, errp); + if (offset < 0) { + return offset; + } + + memcpy(dev->config + offset + PCI_CAP_FLAGS, + (char *)&cap + PCI_CAP_FLAGS, + cap_len - PCI_CAP_FLAGS); + return 0; +} + static const TypeInfo pci_bridge_type_info =3D { .name =3D TYPE_PCI_BRIDGE, .parent =3D TYPE_PCI_DEVICE, diff --git a/include/hw/pci/pci_bridge.h b/include/hw/pci/pci_bridge.h index ff7cbaa..2d8c635 100644 --- a/include/hw/pci/pci_bridge.h +++ b/include/hw/pci/pci_bridge.h @@ -67,4 +67,28 @@ void pci_bridge_map_irq(PCIBridge *br, const char* bus_n= ame, #define PCI_BRIDGE_CTL_DISCARD_STATUS 0x400 /* Discard timer status */ #define PCI_BRIDGE_CTL_DISCARD_SERR 0x800 /* Discard timer SERR# enable */ =20 +typedef struct PCIBridgeQemuCap { + uint8_t id; /* Standard PCI capability header field */ + uint8_t next; /* Standard PCI capability header field */ + uint8_t len; /* Standard PCI vendor-specific capability header fiel= d */ + uint8_t type; /* Red Hat vendor-specific capability type. + Types are defined with REDHAT_PCI_CAP_ prefix */ + + uint32_t bus_res; /* Minimum number of buses to reserve */ + uint64_t io; /* IO space to reserve */ + uint32_t mem; /* Non-prefetchable memory to reserve */ + /* This two fields are mutually exclusive */ + uint32_t mem_pref_32; /* Prefetchable memory to reserve (32-bit MMIO) = */ + uint64_t mem_pref_64; /* Prefetchable memory to reserve (64-bit MMIO) = */ +} PCIBridgeQemuCap; + +#define REDHAT_PCI_CAP_RESOURCE_RESERVE 1 + +int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset, + uint32_t bus_reserve, uint64_t io_reserve, + uint32_t mem_non_pref_reserve, + uint32_t mem_pref_32_reserve, + uint64_t mem_pref_64_reserve, + Error **errp); + #endif /* QEMU_PCI_BRIDGE_H */ --=20 2.7.4 _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios