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[109.173.19.108]) by smtp.gmail.com with ESMTPSA id r196sm1050903lfe.38.2017.08.13.09.03.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 13 Aug 2017 09:03:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=TFomx0NMTRN0NBsK8aajaP1YZGV03jyIyZhuYmQYTTo=; b=hu++bvIFibbyE9q/oL5SEZ2an4610T94NLdDDZCJK7P5zWYWq3G/tKnnZa/AMRkf5R LQWD/cLURbhO4NMdDcrKC1D8FKjzd7puIbjyaJUYiZ+DEkRhppGfvSPcohCNEQ04leGV l36wk0NM7ayPczgzwb4c4VxvyLM1k0AmB/V4iMGNU1aKT4Jgfoxgp6RO0b26sZA8pAT5 3u2p0pd8falfKQqI111Q6MRdXQ4F92bbGWlJofQHpUeHAsTBGLveelCcctYcLzmDdL8m WbqWimhovWuElYX1timjpWJ0U9WbZPeAEYq2m20fAITOvozBfYb/IJZhUUyV2RvWALPx C51g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=TFomx0NMTRN0NBsK8aajaP1YZGV03jyIyZhuYmQYTTo=; b=ZeA5NxPzrPVc8FlAUGDDmoRuqvT+dSeshgRIj/j8rsLeFFKxcaS6j51P3lXb/kYKdS B9vgdIuZIaWToj6AUQb+CgjZe8h1RqZRay+zzpu8Z//gtQ7WDIVib15TIBSzs/qs4cdh xuoyk3DXBT6e99jE7grAlaTRZoS0WotBoVfT3+suZS7V8ukZ2wW63+JV/Yp3RePdcXEi xP3vMpf3Hq4vKCyVAo7vroIUTWwdwZGh03PoixkHuCkCeFGbMo53PnUKiG7QTFLjI7li VX41B92qTupNY2/0vXQltVMzcU3Y7bt02qxyRFss3wTNrhImeooHifkUXgyMu5GBXPzD 0+UQ== X-Gm-Message-State: AHYfb5g63JV5jd9kspPvr9Q5XnLt5HomZhiy9Cgawog5KDFAtccaEoT0 fPeTkLld8eOYN4a+ X-Received: by 10.25.221.77 with SMTP id u74mr7628363lfg.29.1502640216255; Sun, 13 Aug 2017 09:03:36 -0700 (PDT) From: Aleksandr Bezzubikov To: seabios@seabios.org Date: Sun, 13 Aug 2017 19:03:22 +0300 Message-Id: <1502640203-15577-3-git-send-email-zuban32s@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1502640203-15577-1-git-send-email-zuban32s@gmail.com> References: <1502640203-15577-1-git-send-email-zuban32s@gmail.com> X-Spam-Score: -1.1 (-) Subject: [SeaBIOS] [PATCH v6 2/3] pci: add QEMU-specific PCI capability structure X-BeenThere: seabios@seabios.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SeaBIOS mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mst@redhat.com, qemu-devel@nongnu.org, kraxel@redhat.com, marcel@redhat.com, lersek@redhat.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: seabios-bounces@seabios.org Sender: "SeaBIOS" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" On PCI init PCI bridge devices may need some extra info about bus number to reserve, IO, memory and prefetchable memory limits. QEMU can provide this with special vendor-specific PCI capability. This capability is intended to be used only for Red Hat PCI bridges, i.e. QEMU cooperation. Signed-off-by: Aleksandr Bezzubikov Reviewed-by: Marcel Apfelbaum --- src/fw/dev-pci.h | 53 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 src/fw/dev-pci.h diff --git a/src/fw/dev-pci.h b/src/fw/dev-pci.h new file mode 100644 index 0000000..0dc5556 --- /dev/null +++ b/src/fw/dev-pci.h @@ -0,0 +1,53 @@ +#ifndef _PCI_CAP_H +#define _PCI_CAP_H + +#include "types.h" + +/* + * + * QEMU-specific vendor(Red Hat)-specific capability. + * It's intended to provide some hints for firmware to init PCI devices. + * + * Its structure is shown below: + * + * Header: + * + * u8 id; Standard PCI Capability Header field + * u8 next; Standard PCI Capability Header field + * u8 len; Standard PCI Capability Header field + * u8 type; Red Hat vendor-specific capability type + * Data: + * + * u32 bus_res; minimum bus number to reserve; + * this is necessary for PCI Express Root Ports + * to support PCI bridges hotplug + * u64 io; IO space to reserve + * u32 mem; non-prefetchable memory to reserve + * + * At most of the following two fields may be set to a value + * different from 0xFF...F: + * u32 prefetchable_mem_32; prefetchable memory to reserve (32-bit MMI= O) + * u64 prefetchable_mem_64; prefetchable memory to reserve (64-bit MMI= O) + * + * If any field value in Data section is 0xFF...F, + * it means that such kind of reservation is not needed and must be ignore= d. + * +*/ + +/* Offset of vendor-specific capability type field */ +#define PCI_CAP_REDHAT_TYPE_OFFSET 3 + +/* List of valid Red Hat vendor-specific capability types */ +#define REDHAT_CAP_RESOURCE_RESERVE 1 + + +/* Offsets of RESOURCE_RESERVE capability fields */ +#define RES_RESERVE_BUS_RES 4 +#define RES_RESERVE_IO 8 +#define RES_RESERVE_MEM 16 +#define RES_RESERVE_PREF_MEM_32 20 +#define RES_RESERVE_PREF_MEM_64 24 +#define RES_RESERVE_CAP_SIZE 32 + +#endif /* _PCI_CAP_H */ + --=20 2.7.4 _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios