From nobody Sat May 10 07:15:41 2025 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) client-ip=80.81.252.135; envelope-from=seabios-bounces@seabios.org; helo=mail.coreboot.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) smtp.mailfrom=seabios-bounces@seabios.org Return-Path: Received: from mail.coreboot.org (mail.coreboot.org [80.81.252.135]) by mx.zohomail.com with SMTPS id 1503011601254126.97786122163643; Thu, 17 Aug 2017 16:13:21 -0700 (PDT) Received: from [127.0.0.1] (helo=ra.coresystems.de) by mail.coreboot.org with esmtp (Exim 4.86_2) (envelope-from ) id 1diTvh-0000gf-Pf; Fri, 18 Aug 2017 01:10:21 +0200 Received: from mail-lf0-f67.google.com ([209.85.215.67]) by mail.coreboot.org with esmtps (TLSv1.2:ECDHE-RSA-AES128-GCM-SHA256:128) (Exim 4.86_2) (envelope-from ) id 1diTvQ-0000Ys-Ah for seabios@seabios.org; Fri, 18 Aug 2017 01:10:20 +0200 Received: by mail-lf0-f67.google.com with SMTP id x16so5240540lfb.4 for ; Thu, 17 Aug 2017 16:12:47 -0700 (PDT) Received: from localhost.localdomain ([93.185.28.201]) by smtp.gmail.com with ESMTPSA id d17sm987659lfl.86.2017.08.17.16.12.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 17 Aug 2017 16:12:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=JkYh3oQ9fyVfBf1WCfQknt9ahHGwgKu5WzdZIV13rjI=; b=CCnU5clB3027mw6hrija/HVoe3/8UtM32LP3seV62dOE+Gpe+sHVdgG2geOlWBQYQA GjcjKr+EdTJclS6Co1L1n+g/uY5eYgVePnKMLoeQPb00dUyv9FFgOZru/zpdmhM5IJ7S 21j0o+KHd8wVSBnBmTmuefOO4z8cje9wMjEcA4j9WfkwljAz62KTVjEIqQ/ioeNWf+lH OYYkGdeVQiMurYCPMADLdNsFGyMBgcP1Xz2abgqmrxDFJy/Maf851XdUX4E9lIwoHWbl P8by3K0y/Q2PK4jNHr4blkpPH1uNxKnBBCDSrUI7X/iAHvGMEhBq427hcgl0PgrQFJ7z k8UA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=JkYh3oQ9fyVfBf1WCfQknt9ahHGwgKu5WzdZIV13rjI=; b=LxGcZVUW5JkCi0V9XiG07Lz9xC1By7MVBnVildFGTsCa02dF6yBNQo7XZsQ8eCrm4v JQdt4FKMfo9wAXnzDFT1jSi8PSMR5cn5uk9oyEGtoCVzdQW1AAMDyD4Ml1FEi2715TyG 6M7maNxkNQb3qkVjT8ziLRARi3yjQfmkgL/4dIZJqhkwQImNFqJekTH8lyIEMIfOKhH+ GmspRsd20Sqw1SFKxqVte6YNjsC28rfO5SIn8WuJpWz9OUnuT0OIOxZEgTABMA2avPK7 CQGp81vOrlqPWW/2ism31+1x8kvylCbM896SJC+SkB3QwXszQUKH906kg8vR7hUsKlY2 HUbQ== X-Gm-Message-State: AHYfb5hu3gIM83itd8ktkABp5EzBtHcjd+nseUSE82XVRnhERqy2iipv rr8ibtFl2efn9JjGysc= X-Received: by 10.25.225.12 with SMTP id y12mr2991185lfg.83.1503011565227; Thu, 17 Aug 2017 16:12:45 -0700 (PDT) From: Aleksandr Bezzubikov To: seabios@seabios.org Date: Fri, 18 Aug 2017 02:12:30 +0300 Message-Id: <1503011551-7246-3-git-send-email-zuban32s@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503011551-7246-1-git-send-email-zuban32s@gmail.com> References: <1503011551-7246-1-git-send-email-zuban32s@gmail.com> X-Spam-Score: -5.4 (-----) Subject: [SeaBIOS] [PATCH v7 2/3] pci: add QEMU-specific PCI capability structure X-BeenThere: seabios@seabios.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SeaBIOS mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mst@redhat.com, qemu-devel@nongnu.org, kraxel@redhat.com, marcel@redhat.com, lersek@redhat.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: seabios-bounces@seabios.org Sender: "SeaBIOS" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" On PCI init PCI bridge devices may need some extra info about bus number to reserve, IO, memory and prefetchable memory limits. QEMU can provide this with special vendor-specific PCI capability. This capability is intended to be used only for Red Hat PCI bridges, i.e. QEMU cooperation. Signed-off-by: Aleksandr Bezzubikov Reviewed-by: Marcel Apfelbaum --- src/fw/dev-pci.h | 53 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 src/fw/dev-pci.h diff --git a/src/fw/dev-pci.h b/src/fw/dev-pci.h new file mode 100644 index 0000000..0dc5556 --- /dev/null +++ b/src/fw/dev-pci.h @@ -0,0 +1,53 @@ +#ifndef _PCI_CAP_H +#define _PCI_CAP_H + +#include "types.h" + +/* + * + * QEMU-specific vendor(Red Hat)-specific capability. + * It's intended to provide some hints for firmware to init PCI devices. + * + * Its structure is shown below: + * + * Header: + * + * u8 id; Standard PCI Capability Header field + * u8 next; Standard PCI Capability Header field + * u8 len; Standard PCI Capability Header field + * u8 type; Red Hat vendor-specific capability type + * Data: + * + * u32 bus_res; minimum bus number to reserve; + * this is necessary for PCI Express Root Ports + * to support PCI bridges hotplug + * u64 io; IO space to reserve + * u32 mem; non-prefetchable memory to reserve + * + * At most of the following two fields may be set to a value + * different from 0xFF...F: + * u32 prefetchable_mem_32; prefetchable memory to reserve (32-bit MMI= O) + * u64 prefetchable_mem_64; prefetchable memory to reserve (64-bit MMI= O) + * + * If any field value in Data section is 0xFF...F, + * it means that such kind of reservation is not needed and must be ignore= d. + * +*/ + +/* Offset of vendor-specific capability type field */ +#define PCI_CAP_REDHAT_TYPE_OFFSET 3 + +/* List of valid Red Hat vendor-specific capability types */ +#define REDHAT_CAP_RESOURCE_RESERVE 1 + + +/* Offsets of RESOURCE_RESERVE capability fields */ +#define RES_RESERVE_BUS_RES 4 +#define RES_RESERVE_IO 8 +#define RES_RESERVE_MEM 16 +#define RES_RESERVE_PREF_MEM_32 20 +#define RES_RESERVE_PREF_MEM_64 24 +#define RES_RESERVE_CAP_SIZE 32 + +#endif /* _PCI_CAP_H */ + --=20 2.7.4 _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios