From nobody Sat May 10 07:13:34 2025 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) client-ip=80.81.252.135; envelope-from=seabios-bounces@seabios.org; helo=mail.coreboot.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) smtp.mailfrom=seabios-bounces@seabios.org Return-Path: Received: from mail.coreboot.org (mail.coreboot.org [80.81.252.135]) by mx.zohomail.com with SMTPS id 1503012857071731.4645352896143; Thu, 17 Aug 2017 16:34:17 -0700 (PDT) Received: from [127.0.0.1] (helo=ra.coresystems.de) by mail.coreboot.org with esmtp (Exim 4.86_2) (envelope-from ) id 1diUFi-0003aO-4o; Fri, 18 Aug 2017 01:31:02 +0200 Received: from mail-lf0-f66.google.com ([209.85.215.66]) by mail.coreboot.org with esmtps (TLSv1.2:ECDHE-RSA-AES128-GCM-SHA256:128) (Exim 4.86_2) (envelope-from ) id 1diUFU-0003Wo-Hq for seabios@seabios.org; Fri, 18 Aug 2017 01:31:00 +0200 Received: by mail-lf0-f66.google.com with SMTP id w199so5253662lff.2 for ; Thu, 17 Aug 2017 16:33:31 -0700 (PDT) Received: from localhost.localdomain ([93.185.28.201]) by smtp.gmail.com with ESMTPSA id 96sm925433ljb.60.2017.08.17.16.33.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 17 Aug 2017 16:33:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=JkYh3oQ9fyVfBf1WCfQknt9ahHGwgKu5WzdZIV13rjI=; b=r2dZFwSQCC3ZLHrNYwb6V/P6fml6154gV7t/vlil3tOfmCWoSdnH6vtsd6GwtNXKH7 bye7k2P3wHYM8H45U/P9gSN2/q8KnLXpmUM/+Ik4TD64/5TkG2jxDGMuaXNnI0LNd+74 zP0IPdkOVWt3HLE06QdmTqUedSJZeu80Ezk4alRDk39RuHkSjkRcUkit6jYZIJHd1TBm pOFML8gXjWjou+hzqvrgthaH0O1ilyOyOesBl3LhhG4+F2ipr9Wp92y9FydhK9lKvT+a Kxa/rVwZINzN9PdDjwJovA5VPB7d9IIygfgpTJt7ZEE7y6Ejnkvat7iDl+DfMFA98VQb 0tMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=JkYh3oQ9fyVfBf1WCfQknt9ahHGwgKu5WzdZIV13rjI=; b=DjMQUlP3I3cmjLVdg+gyCcWgTn8rPpV32DpP1FafrpW+iUe40+iPgLZYPz1qiX92dR PGt2mmH/WIpPkPaA0ox0Bsz9fsn4cY72I9sHuGs/gHbjZcYj/RJAk+OeY6T2G0HCLtSx Ejr2Dlbhkp5mhUzC1uefMN7RIvwt/4N5jj4w4HzB1dnaqdOOn6vj7EnV560UpNbTNM24 xiqZnPsvqA8ZVO2VNqep8APm19r0jAp2XlqICiywEs764y9OdiKzkbEEnN4mXeP5Lzl3 C1og1vhySoxLb38kaOwFk1uIsAwETkrSV5fgGvvfjLmpLjWzmjlWfVXCjb+atWEemU8f IrdA== X-Gm-Message-State: AHYfb5jPalgxWaHdS1ozuHr2vIbvCybnl4BhKdXvUpcqsYEqD0y97eJi ymqfbxHQqGsqmJ7Lgj8= X-Received: by 10.25.215.21 with SMTP id o21mr2992625lfg.105.1503012809442; Thu, 17 Aug 2017 16:33:29 -0700 (PDT) From: Aleksandr Bezzubikov To: seabios@seabios.org Date: Fri, 18 Aug 2017 02:33:20 +0300 Message-Id: <1503012801-10855-3-git-send-email-zuban32s@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503012801-10855-1-git-send-email-zuban32s@gmail.com> References: <1503012801-10855-1-git-send-email-zuban32s@gmail.com> X-Spam-Score: -4.5 (----) Subject: [SeaBIOS] [PATCH RESEND v7 2/3] pci: add QEMU-specific PCI capability structure X-BeenThere: seabios@seabios.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SeaBIOS mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mst@redhat.com, qemu-devel@nongnu.org, kraxel@redhat.com, marcel@redhat.com, lersek@redhat.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: seabios-bounces@seabios.org Sender: "SeaBIOS" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" On PCI init PCI bridge devices may need some extra info about bus number to reserve, IO, memory and prefetchable memory limits. QEMU can provide this with special vendor-specific PCI capability. This capability is intended to be used only for Red Hat PCI bridges, i.e. QEMU cooperation. Signed-off-by: Aleksandr Bezzubikov Reviewed-by: Marcel Apfelbaum --- src/fw/dev-pci.h | 53 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 src/fw/dev-pci.h diff --git a/src/fw/dev-pci.h b/src/fw/dev-pci.h new file mode 100644 index 0000000..0dc5556 --- /dev/null +++ b/src/fw/dev-pci.h @@ -0,0 +1,53 @@ +#ifndef _PCI_CAP_H +#define _PCI_CAP_H + +#include "types.h" + +/* + * + * QEMU-specific vendor(Red Hat)-specific capability. + * It's intended to provide some hints for firmware to init PCI devices. + * + * Its structure is shown below: + * + * Header: + * + * u8 id; Standard PCI Capability Header field + * u8 next; Standard PCI Capability Header field + * u8 len; Standard PCI Capability Header field + * u8 type; Red Hat vendor-specific capability type + * Data: + * + * u32 bus_res; minimum bus number to reserve; + * this is necessary for PCI Express Root Ports + * to support PCI bridges hotplug + * u64 io; IO space to reserve + * u32 mem; non-prefetchable memory to reserve + * + * At most of the following two fields may be set to a value + * different from 0xFF...F: + * u32 prefetchable_mem_32; prefetchable memory to reserve (32-bit MMI= O) + * u64 prefetchable_mem_64; prefetchable memory to reserve (64-bit MMI= O) + * + * If any field value in Data section is 0xFF...F, + * it means that such kind of reservation is not needed and must be ignore= d. + * +*/ + +/* Offset of vendor-specific capability type field */ +#define PCI_CAP_REDHAT_TYPE_OFFSET 3 + +/* List of valid Red Hat vendor-specific capability types */ +#define REDHAT_CAP_RESOURCE_RESERVE 1 + + +/* Offsets of RESOURCE_RESERVE capability fields */ +#define RES_RESERVE_BUS_RES 4 +#define RES_RESERVE_IO 8 +#define RES_RESERVE_MEM 16 +#define RES_RESERVE_PREF_MEM_32 20 +#define RES_RESERVE_PREF_MEM_64 24 +#define RES_RESERVE_CAP_SIZE 32 + +#endif /* _PCI_CAP_H */ + --=20 2.7.4 _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios