From nobody Sat May 10 07:13:34 2025 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) client-ip=80.81.252.135; envelope-from=seabios-bounces@seabios.org; helo=mail.coreboot.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) smtp.mailfrom=seabios-bounces@seabios.org Return-Path: Received: from mail.coreboot.org (mail.coreboot.org [80.81.252.135]) by mx.zohomail.com with SMTPS id 1503012840165507.6558509111386; Thu, 17 Aug 2017 16:34:00 -0700 (PDT) Received: from [127.0.0.1] (helo=ra.coresystems.de) by mail.coreboot.org with esmtp (Exim 4.86_2) (envelope-from ) id 1diUFk-0003b8-St; Fri, 18 Aug 2017 01:31:04 +0200 Received: from mail-lf0-f65.google.com ([209.85.215.65]) by mail.coreboot.org with esmtps (TLSv1.2:ECDHE-RSA-AES128-GCM-SHA256:128) (Exim 4.86_2) (envelope-from ) id 1diUFW-0003Wv-8Q for seabios@seabios.org; Fri, 18 Aug 2017 01:31:03 +0200 Received: by mail-lf0-f65.google.com with SMTP id w199so5253684lff.2 for ; Thu, 17 Aug 2017 16:33:32 -0700 (PDT) Received: from localhost.localdomain ([93.185.28.201]) by smtp.gmail.com with ESMTPSA id 96sm925433ljb.60.2017.08.17.16.33.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 17 Aug 2017 16:33:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=XVrjkMjSBHGU3vTwqeeaEJwQuYGMHj1tzF9U3+/6BnE=; b=uipRK2nNpZRy+UuFmL4l+6kZV7HQVjzjA2LeapwYr9TlTTQlrBa2zVXy+j3Q5zlMSc 49IfRp8hP3ZCOnEWbVYjvxPpVtd4N7mbpjeWWijXdCdNW2URfy5uIFhIY/7+6Tu5njcX EICU3bAX3ecGWWJiKhIl0N9u6qcpyaPTPrj+g9hmMhcvctEUJUSQD86LRT/ZLruHXxHU Gk5/JWSWhI53NofaXy0IJo0wPLpRykpJEyqtVLs6MtKT116qxpJFn4KT6x2uo/MnwkuP K6ts1lO3eYqXzOIOG9peqsQScMJ2CvDjwQlalXzam8zirojFxgqBia3NGJF68ZrdrxhI F1VA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=XVrjkMjSBHGU3vTwqeeaEJwQuYGMHj1tzF9U3+/6BnE=; b=Qjqywwd/ai9GHAtZDAUXDIinzMKe340ywzRZNXz9IB0G0meawSvytCSn34djzgaKj4 BSZA+SAdIKCo2bcelvYnSEuCzt5nMu1Glg0IVZhynr1LcAIPHAEX98wz369MdDrurSqG zo/1Q0e+eYCfpds0+vY0zWFE3eOziDYPOp6LeHobko7Nt6MMwK19Zz3oiZMJV1zEP1XX Rmo3Ame2Ra9aB2F9hoE9Pkk2nGlfiGpd5HlanS6cd5os+WimDh+HOa9QECwws7DAlVlD dSJzx2xCbeuVlkHjNndJAU7bp8pHNYuuQV/AQYk2lAoIAtmvVjQqBBfGvhuDq4W1W4ky ZF6Q== X-Gm-Message-State: AHYfb5iKBVYNRY8g8od+fcOzoq6d3++/m14EtHh5ecfvmrSkWhXABmJR tJo5PNDYMP37fyaOVm4= X-Received: by 10.46.64.74 with SMTP id n71mr2595248lja.69.1503012811131; Thu, 17 Aug 2017 16:33:31 -0700 (PDT) From: Aleksandr Bezzubikov To: seabios@seabios.org Date: Fri, 18 Aug 2017 02:33:21 +0300 Message-Id: <1503012801-10855-4-git-send-email-zuban32s@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503012801-10855-1-git-send-email-zuban32s@gmail.com> References: <1503012801-10855-1-git-send-email-zuban32s@gmail.com> X-Spam-Score: -4.5 (----) Subject: [SeaBIOS] [PATCH RESEND v7 3/3] pci: enable RedHat PCI bridges to reserve additional resources on PCI init X-BeenThere: seabios@seabios.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SeaBIOS mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mst@redhat.com, qemu-devel@nongnu.org, kraxel@redhat.com, marcel@redhat.com, lersek@redhat.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: seabios-bounces@seabios.org Sender: "SeaBIOS" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" In case of Red Hat Generic PCIE Root Port reserve additional buses and/or IO/MEM/PREF space, which values are provided in a vendor-specific ca= pability. Signed-off-by: Aleksandr Bezzubikov Reviewed-by: Marcel Apfelbaum --- src/fw/pciinit.c | 106 +++++++++++++++++++++++++++++++++++++++++++++++++++= +--- src/hw/pci_ids.h | 3 ++ 2 files changed, 105 insertions(+), 4 deletions(-) diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c index 864954f..7f0e439 100644 --- a/src/fw/pciinit.c +++ b/src/fw/pciinit.c @@ -15,6 +15,7 @@ #include "hw/pcidevice.h" // pci_probe_devices #include "hw/pci_ids.h" // PCI_VENDOR_ID_INTEL #include "hw/pci_regs.h" // PCI_COMMAND +#include "fw/dev-pci.h" // REDHAT_CAP_RESOURCE_RESERVE #include "list.h" // struct hlist_node #include "malloc.h" // free #include "output.h" // dprintf @@ -522,6 +523,32 @@ static void pci_bios_init_platform(void) } } =20 +static u8 pci_find_resource_reserve_capability(u16 bdf) +{ + if (pci_config_readw(bdf, PCI_VENDOR_ID) =3D=3D PCI_VENDOR_ID_REDHAT && + pci_config_readw(bdf, PCI_DEVICE_ID) =3D=3D + PCI_DEVICE_ID_REDHAT_ROOT_PORT) { + u8 cap =3D 0; + do { + cap =3D pci_find_capability(bdf, PCI_CAP_ID_VNDR, cap); + } while (cap && + pci_config_readb(bdf, cap + PCI_CAP_REDHAT_TYPE_OFFSET) != =3D + REDHAT_CAP_RESOURCE_RESERVE); + if (cap) { + u8 cap_len =3D pci_config_readb(bdf, cap + PCI_CAP_FLAGS); + if (cap_len < RES_RESERVE_CAP_SIZE) { + dprintf(1, "PCI: QEMU resource reserve cap length %d is in= valid\n", + cap_len); + } + } else { + dprintf(1, "PCI: invalid QEMU resource reserve cap offset\n"); + } + return cap; + } else { + dprintf(1, "PCI: QEMU resource reserve cap not found\n"); + return 0; + } +} =20 /**************************************************************** * Bus initialization @@ -578,9 +605,33 @@ pci_bios_init_bus_rec(int bus, u8 *pci_bus) pci_bios_init_bus_rec(secbus, pci_bus); =20 if (subbus !=3D *pci_bus) { + u8 res_bus =3D *pci_bus; + u8 cap =3D pci_find_resource_reserve_capability(bdf); + + if (cap) { + u32 tmp_res_bus =3D pci_config_readl(bdf, + cap + RES_RESERVE_BUS_RES); + if (tmp_res_bus !=3D (u32)-1) { + res_bus =3D tmp_res_bus & 0xFF; + if ((u8)(res_bus + secbus) < secbus || + (u8)(res_bus + secbus) < res_bus) { + dprintf(1, "PCI: bus_reserve value %d is invalid\n= ", + res_bus); + res_bus =3D 0; + } + } + if (secbus + res_bus > *pci_bus) { + dprintf(1, "PCI: QEMU resource reserve cap: bus =3D %u= \n", + res_bus); + res_bus =3D secbus + res_bus; + } else { + res_bus =3D *pci_bus; + } + } dprintf(1, "PCI: subordinate bus =3D 0x%x -> 0x%x\n", - subbus, *pci_bus); - subbus =3D *pci_bus; + subbus, res_bus); + subbus =3D res_bus; + *pci_bus =3D res_bus; } else { dprintf(1, "PCI: subordinate bus =3D 0x%x\n", subbus); } @@ -844,20 +895,67 @@ static int pci_bios_check_devices(struct pci_bus *bus= ses) */ parent =3D &busses[0]; int type; - u8 pcie_cap =3D pci_find_capability(s->bus_dev->bdf, PCI_CAP_ID_EX= P, 0); + u16 bdf =3D s->bus_dev->bdf; + u8 pcie_cap =3D pci_find_capability(bdf, PCI_CAP_ID_EXP, 0); + u8 qemu_cap =3D pci_find_resource_reserve_capability(bdf); + int hotplug_support =3D pci_bus_hotplug_support(s, pcie_cap); for (type =3D 0; type < PCI_REGION_TYPE_COUNT; type++) { u64 align =3D (type =3D=3D PCI_REGION_TYPE_IO) ? PCI_BRIDGE_IO_MIN : PCI_BRIDGE_MEM_MIN; if (!pci_bridge_has_region(s->bus_dev, type)) continue; + u64 size =3D 0; + if (qemu_cap) { + u32 tmp_size; + u64 tmp_size_64; + switch(type) { + case PCI_REGION_TYPE_IO: + tmp_size_64 =3D (pci_config_readl(bdf, qemu_cap + RES_= RESERVE_IO) | + (u64)pci_config_readl(bdf, qemu_cap + RES_RESE= RVE_IO + 4) << 32); + if (tmp_size_64 !=3D (u64)-1) { + size =3D tmp_size_64; + } + break; + case PCI_REGION_TYPE_MEM: + tmp_size =3D pci_config_readl(bdf, qemu_cap + RES_RESE= RVE_MEM); + if (tmp_size !=3D (u32)-1) { + size =3D tmp_size; + } + break; + case PCI_REGION_TYPE_PREFMEM: + tmp_size =3D pci_config_readl(bdf, qemu_cap + RES_RESE= RVE_PREF_MEM_32); + tmp_size_64 =3D (pci_config_readl(bdf, qemu_cap + RES_= RESERVE_PREF_MEM_64) | + (u64)pci_config_readl(bdf, qemu_cap + RES_RESE= RVE_PREF_MEM_64 + 4) << 32); + if (tmp_size !=3D (u32)-1 && tmp_size_64 =3D=3D (u64)-= 1) { + size =3D tmp_size; + } else if (tmp_size =3D=3D (u32)-1 && tmp_size_64 !=3D= (u64)-1) { + size =3D tmp_size_64; + } else if (tmp_size !=3D (u32)-1 && tmp_size_64 !=3D (= u64)-1) { + dprintf(1, "PCI: resource reserve cap PREF32 and P= REF64" + " conflict\n"); + } + break; + default: + break; + } + } if (pci_region_align(&s->r[type]) > align) align =3D pci_region_align(&s->r[type]); u64 sum =3D pci_region_sum(&s->r[type]); int resource_optional =3D pcie_cap && (type =3D=3D PCI_REGION_= TYPE_IO); if (!sum && hotplug_support && !resource_optional) sum =3D align; /* reserve min size for hot-plug */ - u64 size =3D ALIGN(sum, align); + if (size > sum) { + dprintf(1, "PCI: QEMU resource reserve cap: " + "size %08llx type %s\n", + size, region_type_name[type]); + if (type !=3D PCI_REGION_TYPE_IO) { + size =3D ALIGN(size, align); + } + } else { + size =3D ALIGN(sum, align); + } int is64 =3D pci_bios_bridge_region_is64(&s->r[type], s->bus_dev, type); // entry->bar is -1 if the entry represents a bridge region diff --git a/src/hw/pci_ids.h b/src/hw/pci_ids.h index 4ac73b4..38fa2ca 100644 --- a/src/hw/pci_ids.h +++ b/src/hw/pci_ids.h @@ -2263,6 +2263,9 @@ #define PCI_DEVICE_ID_KORENIX_JETCARDF0 0x1600 #define PCI_DEVICE_ID_KORENIX_JETCARDF1 0x16ff =20 +#define PCI_VENDOR_ID_REDHAT 0x1b36 +#define PCI_DEVICE_ID_REDHAT_ROOT_PORT 0x000C + #define PCI_VENDOR_ID_TEKRAM 0x1de1 #define PCI_DEVICE_ID_TEKRAM_DC290 0xdc29 =20 --=20 2.7.4 _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios