From nobody Sat May 10 07:30:07 2025 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) client-ip=80.81.252.135; envelope-from=seabios-bounces@seabios.org; helo=mail.coreboot.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) smtp.mailfrom=seabios-bounces@seabios.org Return-Path: Received: from mail.coreboot.org (mail.coreboot.org [80.81.252.135]) by mx.zohomail.com with SMTPS id 1503013040206491.9854109811117; Thu, 17 Aug 2017 16:37:20 -0700 (PDT) Received: from [127.0.0.1] (helo=ra.coresystems.de) by mail.coreboot.org with esmtp (Exim 4.86_2) (envelope-from ) id 1diUIy-0004Ct-7R; Fri, 18 Aug 2017 01:34:24 +0200 Received: from mail-lf0-f67.google.com ([209.85.215.67]) by mail.coreboot.org with esmtps (TLSv1.2:ECDHE-RSA-AES128-GCM-SHA256:128) (Exim 4.86_2) (envelope-from ) id 1diUIo-0004BR-LW for seabios@seabios.org; Fri, 18 Aug 2017 01:34:22 +0200 Received: by mail-lf0-f67.google.com with SMTP id x16so5260802lfb.4 for ; Thu, 17 Aug 2017 16:36:57 -0700 (PDT) Received: from localhost.localdomain ([93.185.28.201]) by smtp.gmail.com with ESMTPSA id y1sm903381lja.86.2017.08.17.16.36.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 17 Aug 2017 16:36:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=EOoQ+KUj10XCtwV66P/xX9bI5anyDN6ckJ7Mwh+l138=; b=XGvuEWJLBin6/ZkFrC2eQzsGGtmORMwqRCQSSg2QZLXe5wUkQJQ6l4F8oh49kGy4k2 v/IuvyczNh4iurPd9k4yfR0Hcq2zA82Glj7rw7eF/3Y6A8IRgivx/mUG3J6Xa8k5vYMp lU8JufLDYnrPueIMfGq9Hu4hhNYUbUeWchl1QQq1mSj8H136riGUa9hYny6sbBKJ8dmp AVrMiy4AQU4Tt+XaO54I4QyIGF7ZzZuQd4FZ4aH27wkYtbCwvnW9iXqFJnv8/kW3ku1P Xw98X+U2yz6nQhjmOqEUuOB8oRzE1XH1D8Bs8hKMM5Chbp5ScT0UAXT5wb1wpY706Gk7 EKYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=EOoQ+KUj10XCtwV66P/xX9bI5anyDN6ckJ7Mwh+l138=; b=OVapIu0CZy/v+PXSkXocjuX5X+xw2qr4VjHyxPtcY7svqR9a6Of7L9qKYf2voneEE8 8XCUWgugkCXZHv5LOltoqXSZ4VeWhgsUQi3BuhdY1WFVZjPdHQmOwuq1leJTfI+0150V a+s3POdUtG2N9HcpVpyX4YjAye9urWW4s+ZGB4+A12cWidvOE1YYfF2McxHX/vewIIq/ jg6ui3HYJNIBlR+6IaLJJEVyv+RtL5Sn88CfNXzOQIEm1IOAhgUAxfw63QWN2QJWJyN4 eCWl3G2ZmAGgEzYT+1jdn6UO+RZZuegepBlMYh8z8vWvCoJXRa5jSVt4CibVZ2EZNFfw DTPQ== X-Gm-Message-State: AHYfb5hvLCB4o245q+GIdEr7ij1TULiIIN2rUfI7MUK6JPUYM1AIptn1 Jc/Gj27G/ElyIA== X-Received: by 10.25.216.212 with SMTP id r81mr2282654lfi.26.1503013015857; Thu, 17 Aug 2017 16:36:55 -0700 (PDT) From: Aleksandr Bezzubikov To: qemu-devel@nongnu.org Date: Fri, 18 Aug 2017 02:36:47 +0300 Message-Id: <1503013010-11500-2-git-send-email-zuban32s@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503013010-11500-1-git-send-email-zuban32s@gmail.com> References: <1503013010-11500-1-git-send-email-zuban32s@gmail.com> X-Spam-Score: -4.5 (----) Subject: [SeaBIOS] [PATCH v7 1/4] hw/pci: introduce pcie-pci-bridge device X-BeenThere: seabios@seabios.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SeaBIOS mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marcel@redhat.com, seabios@seabios.org, lersek@redhat.com, mst@redhat.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: seabios-bounces@seabios.org Sender: "SeaBIOS" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Introduce a new PCIExpress-to-PCI Bridge device, which is a hot-pluggable PCI Express device and supports devices hot-plug with SHPC. This device is intended to replace the DMI-to-PCI Bridge. Signed-off-by: Aleksandr Bezzubikov Reviewed-by: Marcel Apfelbaum --- hw/pci-bridge/Makefile.objs | 2 +- hw/pci-bridge/pcie_pci_bridge.c | 192 ++++++++++++++++++++++++++++++++++++= ++++ include/hw/pci/pci.h | 1 + 3 files changed, 194 insertions(+), 1 deletion(-) create mode 100644 hw/pci-bridge/pcie_pci_bridge.c diff --git a/hw/pci-bridge/Makefile.objs b/hw/pci-bridge/Makefile.objs index c4683cf..666db37 100644 --- a/hw/pci-bridge/Makefile.objs +++ b/hw/pci-bridge/Makefile.objs @@ -1,4 +1,4 @@ -common-obj-y +=3D pci_bridge_dev.o +common-obj-y +=3D pci_bridge_dev.o pcie_pci_bridge.o common-obj-$(CONFIG_PCIE_PORT) +=3D pcie_root_port.o gen_pcie_root_port.o common-obj-$(CONFIG_PXB) +=3D pci_expander_bridge.o common-obj-$(CONFIG_XIO3130) +=3D xio3130_upstream.o xio3130_downstream.o diff --git a/hw/pci-bridge/pcie_pci_bridge.c b/hw/pci-bridge/pcie_pci_bridg= e.c new file mode 100644 index 0000000..9aa5cc3 --- /dev/null +++ b/hw/pci-bridge/pcie_pci_bridge.c @@ -0,0 +1,192 @@ +/* + * QEMU Generic PCIE-PCI Bridge + * + * Copyright (c) 2017 Aleksandr Bezzubikov + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/pci/pci.h" +#include "hw/pci/pci_bus.h" +#include "hw/pci/pci_bridge.h" +#include "hw/pci/msi.h" +#include "hw/pci/shpc.h" +#include "hw/pci/slotid_cap.h" + +typedef struct PCIEPCIBridge { + /*< private >*/ + PCIBridge parent_obj; + + OnOffAuto msi; + MemoryRegion shpc_bar; + /*< public >*/ +} PCIEPCIBridge; + +#define TYPE_PCIE_PCI_BRIDGE_DEV "pcie-pci-bridge" +#define PCIE_PCI_BRIDGE_DEV(obj) \ + OBJECT_CHECK(PCIEPCIBridge, (obj), TYPE_PCIE_PCI_BRIDGE_DEV) + +static void pcie_pci_bridge_realize(PCIDevice *d, Error **errp) +{ + PCIBridge *br =3D PCI_BRIDGE(d); + PCIEPCIBridge *pcie_br =3D PCIE_PCI_BRIDGE_DEV(d); + int rc, pos; + + pci_bridge_initfn(d, TYPE_PCI_BUS); + + d->config[PCI_INTERRUPT_PIN] =3D 0x1; + memory_region_init(&pcie_br->shpc_bar, OBJECT(d), "shpc-bar", + shpc_bar_size(d)); + rc =3D shpc_init(d, &br->sec_bus, &pcie_br->shpc_bar, 0, errp); + if (rc) { + goto error; + } + + rc =3D pcie_cap_init(d, 0, PCI_EXP_TYPE_PCI_BRIDGE, 0, errp); + if (rc < 0) { + goto cap_error; + } + + pos =3D pci_add_capability(d, PCI_CAP_ID_PM, 0, PCI_PM_SIZEOF, errp); + if (pos < 0) { + goto pm_error; + } + d->exp.pm_cap =3D pos; + pci_set_word(d->config + pos + PCI_PM_PMC, 0x3); + + pcie_cap_arifwd_init(d); + pcie_cap_deverr_init(d); + + rc =3D pcie_aer_init(d, PCI_ERR_VER, 0x100, PCI_ERR_SIZEOF, errp); + if (rc < 0) { + goto aer_error; + } + + if (pcie_br->msi !=3D ON_OFF_AUTO_OFF) { + rc =3D msi_init(d, 0, 1, true, true, errp); + if (rc < 0) { + goto msi_error; + } + } + pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY | + PCI_BASE_ADDRESS_MEM_TYPE_64, &pcie_br->shpc_bar); + return; + +msi_error: + pcie_aer_exit(d); +aer_error: +pm_error: + pcie_cap_exit(d); +cap_error: + shpc_free(d); +error: + pci_bridge_exitfn(d); +} + +static void pcie_pci_bridge_exit(PCIDevice *d) +{ + PCIEPCIBridge *bridge_dev =3D PCIE_PCI_BRIDGE_DEV(d); + pcie_cap_exit(d); + shpc_cleanup(d, &bridge_dev->shpc_bar); + pci_bridge_exitfn(d); +} + +static void pcie_pci_bridge_reset(DeviceState *qdev) +{ + PCIDevice *d =3D PCI_DEVICE(qdev); + pci_bridge_reset(qdev); + msi_reset(d); + shpc_reset(d); +} + +static void pcie_pci_bridge_write_config(PCIDevice *d, + uint32_t address, uint32_t val, int len) +{ + pci_bridge_write_config(d, address, val, len); + msi_write_config(d, address, val, len); + shpc_cap_write_config(d, address, val, len); +} + +static Property pcie_pci_bridge_dev_properties[] =3D { + DEFINE_PROP_ON_OFF_AUTO("msi", PCIEPCIBridge, msi, ON_OFF_AUTO_ON), + DEFINE_PROP_END_OF_LIST(), +}; + +static const VMStateDescription pcie_pci_bridge_dev_vmstate =3D { + .name =3D TYPE_PCIE_PCI_BRIDGE_DEV, + .fields =3D (VMStateField[]) { + VMSTATE_PCI_DEVICE(parent_obj, PCIBridge), + SHPC_VMSTATE(shpc, PCIDevice, NULL), + VMSTATE_END_OF_LIST() + } +}; + +static void pcie_pci_bridge_hotplug_cb(HotplugHandler *hotplug_dev, + DeviceState *dev, Error **errp) +{ + PCIDevice *pci_hotplug_dev =3D PCI_DEVICE(hotplug_dev); + + if (!shpc_present(pci_hotplug_dev)) { + error_setg(errp, "standard hotplug controller has been disabled fo= r " + "this %s", TYPE_PCIE_PCI_BRIDGE_DEV); + return; + } + shpc_device_hotplug_cb(hotplug_dev, dev, errp); +} + +static void pcie_pci_bridge_hot_unplug_request_cb(HotplugHandler *hotplug_= dev, + DeviceState *dev, + Error **errp) +{ + PCIDevice *pci_hotplug_dev =3D PCI_DEVICE(hotplug_dev); + + if (!shpc_present(pci_hotplug_dev)) { + error_setg(errp, "standard hotplug controller has been disabled fo= r " + "this %s", TYPE_PCIE_PCI_BRIDGE_DEV); + return; + } + shpc_device_hot_unplug_request_cb(hotplug_dev, dev, errp); +} + +static void pcie_pci_bridge_class_init(ObjectClass *klass, void *data) +{ + PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); + DeviceClass *dc =3D DEVICE_CLASS(klass); + HotplugHandlerClass *hc =3D HOTPLUG_HANDLER_CLASS(klass); + + k->is_express =3D 1; + k->is_bridge =3D 1; + k->vendor_id =3D PCI_VENDOR_ID_REDHAT; + k->device_id =3D PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE; + k->realize =3D pcie_pci_bridge_realize; + k->exit =3D pcie_pci_bridge_exit; + k->config_write =3D pcie_pci_bridge_write_config; + dc->vmsd =3D &pcie_pci_bridge_dev_vmstate; + dc->props =3D pcie_pci_bridge_dev_properties; + dc->vmsd =3D &pcie_pci_bridge_dev_vmstate; + dc->reset =3D &pcie_pci_bridge_reset; + set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); + hc->plug =3D pcie_pci_bridge_hotplug_cb; + hc->unplug_request =3D pcie_pci_bridge_hot_unplug_request_cb; +} + +static const TypeInfo pcie_pci_bridge_info =3D { + .name =3D TYPE_PCIE_PCI_BRIDGE_DEV, + .parent =3D TYPE_PCI_BRIDGE, + .instance_size =3D sizeof(PCIEPCIBridge), + .class_init =3D pcie_pci_bridge_class_init, + .interfaces =3D (InterfaceInfo[]) { + { TYPE_HOTPLUG_HANDLER }, + { }, + } +}; + +static void pciepci_register(void) +{ + type_register_static(&pcie_pci_bridge_info); +} + +type_init(pciepci_register); diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index e598b09..b33a34f 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -98,6 +98,7 @@ #define PCI_DEVICE_ID_REDHAT_PXB_PCIE 0x000b #define PCI_DEVICE_ID_REDHAT_PCIE_RP 0x000c #define PCI_DEVICE_ID_REDHAT_XHCI 0x000d +#define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e #define PCI_DEVICE_ID_REDHAT_QXL 0x0100 =20 #define FMT_PCIBUS PRIx64 --=20 2.7.4 _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios