From nobody Sat May 10 07:30:07 2025 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) client-ip=80.81.252.135; envelope-from=seabios-bounces@seabios.org; helo=mail.coreboot.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) smtp.mailfrom=seabios-bounces@seabios.org Return-Path: Received: from mail.coreboot.org (mail.coreboot.org [80.81.252.135]) by mx.zohomail.com with SMTPS id 1503013045825443.5115219517129; Thu, 17 Aug 2017 16:37:25 -0700 (PDT) Received: from [127.0.0.1] (helo=ra.coresystems.de) by mail.coreboot.org with esmtp (Exim 4.86_2) (envelope-from ) id 1diUJ3-0004E7-0o; Fri, 18 Aug 2017 01:34:29 +0200 Received: from mail-lf0-f67.google.com ([209.85.215.67]) by mail.coreboot.org with esmtps (TLSv1.2:ECDHE-RSA-AES128-GCM-SHA256:128) (Exim 4.86_2) (envelope-from ) id 1diUIq-0004BS-49 for seabios@seabios.org; Fri, 18 Aug 2017 01:34:27 +0200 Received: by mail-lf0-f67.google.com with SMTP id x16so5260819lfb.4 for ; Thu, 17 Aug 2017 16:36:58 -0700 (PDT) Received: from localhost.localdomain ([93.185.28.201]) by smtp.gmail.com with ESMTPSA id y1sm903381lja.86.2017.08.17.16.36.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 17 Aug 2017 16:36:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4PaU3I+M2PeTeskvPFhgE9451D/rXcihg6IsfQMCYD8=; b=dck7PCsttfObTTgkQmC7CPqxTDQqRoQuhdGAl4CcZ5q+T6AtPgCiG0wczCxY3IxR7x x9XiJ4YxOrDLl+5Szx6rT/xTtFluZ4hnsrIA3qPpaatpT4pKK1qYH8XDn26WU42l7ytb NJ59iWvZqCcFuws7tsKdxGxf8Ua6ZXdHcha2A6IRjJlZZoPeV06RSu9XSe/4Tan6PBGM UktWdyHmOc7TwNZfS6s6tRPgOaRDItHPMCfSkz8x7STtvSbVtCosLjZuHbhjGiplV+ij Lwuw8eWvrQR4HDj3rCn4DZgqjYib7hFRZUvofiJZdNDihZfGyEI+CzGPbeDTcJ7IhKEb 8+GA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4PaU3I+M2PeTeskvPFhgE9451D/rXcihg6IsfQMCYD8=; b=b3n/OoZFM+cuT5HxMy+vH0ES+qxPTQ51JBQW92hJuFbkbwaX6Ct0j/ieBWNDsyPPPA DV8gg/A0XKrKsi6bX7EssqGEdzkmFkrI+bCojGYBpsi7q6rgrM1iHXMFDp1ZAt4KWZax 1FjcEm/0EDZEzTHMiDP5agwRQdsowypk2RGudjbUiTLPaf1wbhGovdwdXpHcP7si1QrM EPKq+RUxL6f2qxxg7XkwHvAlQcYJQikSVTUboGF4JbAi+h6tWGVX26z6vFe5vCnDa2RR 0fjxM7paDidUGgk7nYbAWSJq5vjhwsJB2IYCvSfD5CDfslzKRwwLapKM90WBmi1XqJ5r dw3A== X-Gm-Message-State: AHYfb5jB4ol8KAlFPLEaPY9TCzFNwl6Amsa122O5jyjrgTcsOfXa5xDQ 2l1VdgxnSBgTKrsIlMw= X-Received: by 10.25.209.148 with SMTP id i142mr2189054lfg.135.1503013017343; Thu, 17 Aug 2017 16:36:57 -0700 (PDT) From: Aleksandr Bezzubikov To: qemu-devel@nongnu.org Date: Fri, 18 Aug 2017 02:36:48 +0300 Message-Id: <1503013010-11500-3-git-send-email-zuban32s@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503013010-11500-1-git-send-email-zuban32s@gmail.com> References: <1503013010-11500-1-git-send-email-zuban32s@gmail.com> X-Spam-Score: -6.4 (------) Subject: [SeaBIOS] [PATCH v7 2/4] hw/pci: introduce bridge-only vendor-specific capability to provide some hints to firmware X-BeenThere: seabios@seabios.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SeaBIOS mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marcel@redhat.com, seabios@seabios.org, lersek@redhat.com, mst@redhat.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: seabios-bounces@seabios.org Sender: "SeaBIOS" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" On PCI init PCI bridges may need some extra info about bus number, IO, memory and prefetchable memory to reserve. QEMU can provide this with a special vendor-specific PCI capability. Signed-off-by: Aleksandr Bezzubikov Reviewed-by: Marcel Apfelbaum --- hw/pci/pci_bridge.c | 46 +++++++++++++++++++++++++++++++++++++++++= ++++ include/hw/pci/pci_bridge.h | 25 ++++++++++++++++++++++++ 2 files changed, 71 insertions(+) diff --git a/hw/pci/pci_bridge.c b/hw/pci/pci_bridge.c index 720119b..17feae5 100644 --- a/hw/pci/pci_bridge.c +++ b/hw/pci/pci_bridge.c @@ -408,6 +408,52 @@ void pci_bridge_map_irq(PCIBridge *br, const char* bus= _name, br->bus_name =3D bus_name; } =20 + +int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset, + uint32_t bus_reserve, uint64_t io_res= erve, + uint32_t mem_non_pref_reserve, + uint32_t mem_pref_32_reserve, + uint64_t mem_pref_64_reserve, + Error **errp) +{ + if (mem_pref_32_reserve !=3D (uint32_t)-1 && + mem_pref_64_reserve !=3D (uint64_t)-1) { + error_setg(errp, + "PCI resource reserve cap: PREF32 and PREF64 conflict"); + return -EINVAL; + } + + if (bus_reserve =3D=3D (uint32_t)-1 && + io_reserve =3D=3D (uint64_t)-1 && + mem_non_pref_reserve =3D=3D (uint32_t)-1 && + mem_pref_32_reserve =3D=3D (uint32_t)-1 && + mem_pref_64_reserve =3D=3D (uint64_t)-1) { + return 0; + } + + size_t cap_len =3D sizeof(PCIBridgeQemuCap); + PCIBridgeQemuCap cap =3D { + .len =3D cap_len, + .type =3D REDHAT_PCI_CAP_RESOURCE_RESERVE, + .bus_res =3D bus_reserve, + .io =3D io_reserve, + .mem =3D mem_non_pref_reserve, + .mem_pref_32 =3D mem_pref_32_reserve, + .mem_pref_64 =3D mem_pref_64_reserve + }; + + int offset =3D pci_add_capability(dev, PCI_CAP_ID_VNDR, + cap_offset, cap_len, errp); + if (offset < 0) { + return offset; + } + + memcpy(dev->config + offset + PCI_CAP_FLAGS, + (char *)&cap + PCI_CAP_FLAGS, + cap_len - PCI_CAP_FLAGS); + return 0; +} + static const TypeInfo pci_bridge_type_info =3D { .name =3D TYPE_PCI_BRIDGE, .parent =3D TYPE_PCI_DEVICE, diff --git a/include/hw/pci/pci_bridge.h b/include/hw/pci/pci_bridge.h index ff7cbaa..1acadc2 100644 --- a/include/hw/pci/pci_bridge.h +++ b/include/hw/pci/pci_bridge.h @@ -67,4 +67,29 @@ void pci_bridge_map_irq(PCIBridge *br, const char* bus_n= ame, #define PCI_BRIDGE_CTL_DISCARD_STATUS 0x400 /* Discard timer status */ #define PCI_BRIDGE_CTL_DISCARD_SERR 0x800 /* Discard timer SERR# enable */ =20 +typedef struct PCIBridgeQemuCap { + uint8_t id; /* Standard PCI capability header field */ + uint8_t next; /* Standard PCI capability header field */ + uint8_t len; /* Standard PCI vendor-specific capability header fiel= d */ + uint8_t type; /* Red Hat vendor-specific capability type. + Types are defined with REDHAT_PCI_CAP_ prefix */ + + uint32_t bus_res; /* Minimum number of buses to reserve */ + uint64_t io; /* IO space to reserve */ + uint32_t mem; /* Non-prefetchable memory to reserve */ + /* At most one of the following two fields may be set to a value + * different from -1 */ + uint32_t mem_pref_32; /* Prefetchable memory to reserve (32-bit MMIO) = */ + uint64_t mem_pref_64; /* Prefetchable memory to reserve (64-bit MMIO) = */ +} PCIBridgeQemuCap; + +#define REDHAT_PCI_CAP_RESOURCE_RESERVE 1 + +int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset, + uint32_t bus_reserve, uint64_t io_reserve, + uint32_t mem_non_pref_reserve, + uint32_t mem_pref_32_reserve, + uint64_t mem_pref_64_reserve, + Error **errp); + #endif /* QEMU_PCI_BRIDGE_H */ --=20 2.7.4 _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios