From nobody Mon Dec 15 23:28:13 2025 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) client-ip=80.81.252.135; envelope-from=seabios-bounces@seabios.org; helo=mail.coreboot.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) smtp.mailfrom=seabios-bounces@seabios.org Return-Path: Received: from mail.coreboot.org (mail.coreboot.org [80.81.252.135]) by mx.zohomail.com with SMTPS id 150301305320289.0866101096484; Thu, 17 Aug 2017 16:37:33 -0700 (PDT) Received: from [127.0.0.1] (helo=ra.coresystems.de) by mail.coreboot.org with esmtp (Exim 4.86_2) (envelope-from ) id 1diUJ7-0004Fm-2f; Fri, 18 Aug 2017 01:34:33 +0200 Received: from mail-lf0-f66.google.com ([209.85.215.66]) by mail.coreboot.org with esmtps (TLSv1.2:ECDHE-RSA-AES128-GCM-SHA256:128) (Exim 4.86_2) (envelope-from ) id 1diUIr-0004Bj-I0 for seabios@seabios.org; Fri, 18 Aug 2017 01:34:31 +0200 Received: by mail-lf0-f66.google.com with SMTP id y15so5240915lfd.5 for ; Thu, 17 Aug 2017 16:37:00 -0700 (PDT) Received: from localhost.localdomain ([93.185.28.201]) by smtp.gmail.com with ESMTPSA id y1sm903381lja.86.2017.08.17.16.36.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 17 Aug 2017 16:36:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2jQ3Y5XNIdBwfg+2/eLzl8VJs2KPUS9AFm6oFlNKrIA=; b=qmlV1xZg9WsJMnKKVTepkBii98tYB1OvE73Ib3m4z4DIzr3d+6VKpg7NAhUxPZ5SXV FCqI8ZFuffqI030kWQDldHYXJOBkWCm1wlvHqO+Z3CMIhU4s9q4F1v8AV/yyvXAPVTfy m0SjZz9Q33fVCAiB4l3CZniKbSdk/P8ABeV8hI7DP7xDYxiVeb/ysKrmf9aSeVHWnXrF MYQ1tyzz5BAfCnqFwcRHWIYQjs1yyyKMrZlccX2CTp+6mYiGgECKUi/jYVi/czzBpYUB FTpQyqICDSDQxlmRM0KrsFG1yZmKTkDQcOKyiXud0DiZpt0FS8XFbQMZ8I/6q2LelX6S GZZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2jQ3Y5XNIdBwfg+2/eLzl8VJs2KPUS9AFm6oFlNKrIA=; b=g7ERjmg2b1Ndbb3PCpV9H43ePwVMAdvidtR2Gi8ASyEss5P2RhaKx+b3Ks4B89e9tQ TM9Smj7SZdFwzBtoF60gYeeiVXmdBumtnz+84YaIRhQtDcYoRDMFtrC3M8Gb9Mkzunn/ laQy/IkeW5xXB/RJn8hAD28plS1cZWKH1rtb7V7rVJWz5O8OQfxCupJyZfstZvU8YhCd deoVXpXmr4oiBB/kZ1VHB54ulQsDfllJNxk6ePvrtvG5VgzTGKm5PzRFjYam1NFO/LTQ YmiwDip2PK6HRjEPSZjwIV1xdpI8WO2Z17ahxZfnDP8hPizJ6STfJ/KwvNvpCHPNyAeN dptg== X-Gm-Message-State: AHYfb5hq4Ad9NOHsWRcQUKjJs2mR8VOU1JBwxq+1PPHK/6GqNbxPV/JO l2QdxYRzm8/S4wSIhPY= X-Received: by 10.46.22.20 with SMTP id w20mr3086679ljd.103.1503013018804; Thu, 17 Aug 2017 16:36:58 -0700 (PDT) From: Aleksandr Bezzubikov To: qemu-devel@nongnu.org Date: Fri, 18 Aug 2017 02:36:49 +0300 Message-Id: <1503013010-11500-4-git-send-email-zuban32s@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503013010-11500-1-git-send-email-zuban32s@gmail.com> References: <1503013010-11500-1-git-send-email-zuban32s@gmail.com> X-Spam-Score: -4.0 (----) Subject: [SeaBIOS] [PATCH v7 3/4] hw/pci: add QEMU-specific PCI capability to the Generic PCI Express Root Port X-BeenThere: seabios@seabios.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SeaBIOS mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marcel@redhat.com, seabios@seabios.org, lersek@redhat.com, mst@redhat.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: seabios-bounces@seabios.org Sender: "SeaBIOS" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" To enable hotplugging of a newly created pcie-pci-bridge, we need to tell firmware (e.g. SeaBIOS) to reserve additional buses or IO/MEM/PREF space for pcie-root-port. Additional bus reservation allows us to hotplug pcie-pci-bridge into this r= oot port. The number of buses and IO/MEM/PREF space to reserve are provided to the de= vice via a corresponding property, and to the firmware via new PCI capability. The properties' default values are -1 to keep default behavior unchanged. Signed-off-by: Aleksandr Bezzubikov Reviewed-by: Marcel Apfelbaum --- hw/pci-bridge/gen_pcie_root_port.c | 36 ++++++++++++++++++++++++++++++++++= ++ include/hw/pci/pcie_port.h | 1 + 2 files changed, 37 insertions(+) diff --git a/hw/pci-bridge/gen_pcie_root_port.c b/hw/pci-bridge/gen_pcie_ro= ot_port.c index cb694d6..ed03ffc 100644 --- a/hw/pci-bridge/gen_pcie_root_port.c +++ b/hw/pci-bridge/gen_pcie_root_port.c @@ -16,6 +16,8 @@ #include "hw/pci/pcie_port.h" =20 #define TYPE_GEN_PCIE_ROOT_PORT "pcie-root-port" +#define GEN_PCIE_ROOT_PORT(obj) \ + OBJECT_CHECK(GenPCIERootPort, (obj), TYPE_GEN_PCIE_ROOT_PORT) =20 #define GEN_PCIE_ROOT_PORT_AER_OFFSET 0x100 #define GEN_PCIE_ROOT_PORT_MSIX_NR_VECTOR 1 @@ -26,6 +28,13 @@ typedef struct GenPCIERootPort { /*< public >*/ =20 bool migrate_msix; + + /* additional resources to reserve on firmware init */ + uint32_t bus_reserve; + uint64_t io_reserve; + uint64_t mem_reserve; + uint64_t pref32_reserve; + uint64_t pref64_reserve; } GenPCIERootPort; =20 static uint8_t gen_rp_aer_vector(const PCIDevice *d) @@ -60,6 +69,24 @@ static bool gen_rp_test_migrate_msix(void *opaque, int v= ersion_id) return rp->migrate_msix; } =20 +static void gen_rp_realize(DeviceState *dev, Error **errp) +{ + PCIDevice *d =3D PCI_DEVICE(dev); + GenPCIERootPort *grp =3D GEN_PCIE_ROOT_PORT(d); + PCIERootPortClass *rpc =3D PCIE_ROOT_PORT_GET_CLASS(d); + + rpc->parent_realize(dev, errp); + + int rc =3D pci_bridge_qemu_reserve_cap_init(d, 0, grp->bus_reserve, + grp->io_reserve, grp->mem_reserve, grp->pref32_reserve, + grp->pref64_reserve, errp); + + if (rc < 0) { + rpc->parent_class.exit(d); + return; + } +} + static const VMStateDescription vmstate_rp_dev =3D { .name =3D "pcie-root-port", .version_id =3D 1, @@ -78,6 +105,11 @@ static const VMStateDescription vmstate_rp_dev =3D { =20 static Property gen_rp_props[] =3D { DEFINE_PROP_BOOL("x-migrate-msix", GenPCIERootPort, migrate_msix, true= ), + DEFINE_PROP_UINT32("bus-reserve", GenPCIERootPort, bus_reserve, -1), + DEFINE_PROP_SIZE("io-reserve", GenPCIERootPort, io_reserve, -1), + DEFINE_PROP_SIZE("mem-reserve", GenPCIERootPort, mem_reserve, -1), + DEFINE_PROP_SIZE("pref32-reserve", GenPCIERootPort, pref32_reserve, -1= ), + DEFINE_PROP_SIZE("pref64-reserve", GenPCIERootPort, pref64_reserve, -1= ), DEFINE_PROP_END_OF_LIST() }; =20 @@ -92,6 +124,10 @@ static void gen_rp_dev_class_init(ObjectClass *klass, v= oid *data) dc->desc =3D "PCI Express Root Port"; dc->vmsd =3D &vmstate_rp_dev; dc->props =3D gen_rp_props; + + rpc->parent_realize =3D dc->realize; + dc->realize =3D gen_rp_realize; + rpc->aer_vector =3D gen_rp_aer_vector; rpc->interrupts_init =3D gen_rp_interrupts_init; rpc->interrupts_uninit =3D gen_rp_interrupts_uninit; diff --git a/include/hw/pci/pcie_port.h b/include/hw/pci/pcie_port.h index 1333266..0736014 100644 --- a/include/hw/pci/pcie_port.h +++ b/include/hw/pci/pcie_port.h @@ -65,6 +65,7 @@ void pcie_chassis_del_slot(PCIESlot *s); =20 typedef struct PCIERootPortClass { PCIDeviceClass parent_class; + DeviceRealize parent_realize; =20 uint8_t (*aer_vector)(const PCIDevice *dev); int (*interrupts_init)(PCIDevice *dev, Error **errp); --=20 2.7.4 _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios